Maxim Integrated Petaluma (MAXREFDES30) ZedBoard - Manual (Page 5)

Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide
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3. Included Files
The top level of the hardware design is a Xilinx PlanAhead™ Project (.PRR) for Xilinx
PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides
FPGA/board net connectivity, and instantiates the wrapper that carries both the Zynq®
Processing System and AXI_MAX11046 custom IP core that interface to the FMC
connector. This is supplied as a Xilinx software development kit (SDK) project that
includes a demonstration software application to evaluate the Petaluma subsystem
reference design. The lower level c-code driver routines are portable to the user’s own
software project.
Figure 2. Block Diagram of FPGA Hardware Design