Appendix a: project structure and key filenames, Trademarks – Maxim Integrated Petaluma (MAXREFDES30) ZedBoard User Manual
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Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide
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6. Appendix A: Project Structure and Key Filenames
Top level folder contains:
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Numerous source and intermediate files (PlanAhead generated)
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top.ppr = main Xilinx PlanAhead project file.
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top.* = the Xilinx PlanAhead top level project folders
SDK Export Folder
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\MAXREFDESX = C Project Folder
\src\MAXREFDESX.c = Main example program
\src\maximDeviceSpecificUtilities.c = driver functions
\src\menu.c = menu functions
\src\utilities.c = generic system and FPGA helper functions
\src\platform.c = low-level routines, Xilinx generated
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\MAXREFDESX_bsp_0 = Board support package
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\arm_system_hw_platform = Hardware platform spcification
Driver folder for the AXI_MAX11046 custom IP core
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\axi_max11046_vX_XX_X\src\axi_max11046.c = driver functions
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\axi_max11046_vX_XX_X\src\axi_max11046.h = driver header file
Pcore folder contains:
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The HDL source files for the AXI_MAX11046 custom IP core
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\axi_max11046_vX_XX_X\hdl\verilog\axi_max11046.v = Top level
design, instantiates library components and user logic
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\axi_max11046_vX_XX_X\hdl\verilog\user_logic.v = User logic module
that implements the MAX11046 ADC SPI interface
7. Trademarks
ARM is a registered trademark and registered service mark of ARM Ltd.
Cortex is a trademark of ARM Ltd.
Eclipse is a trademark of Eclipse Foundation, Inc.
MicroBlaze is a trademark of Xilinx, Inc.
PlanAhead is a trademark of Xilinx, Inc.
Windows is a registered trademark and registered service mark and Windows XP is a
registered trademark of Microsoft Corporation.
Xilinx is a registered trademark and registered service mark of Xilinx, Inc.
ZedBoard is a trademark of ZedBoard.org.
Zynq is a registered trademark of Xilinx, Inc.