Kontron COMe-cTH6 - Manual (Page 35)

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COMe-cTH6 User’s Guide
www.kontron.com
5.8 SPI Bus Interface
The Serial Peripheral Interface (SPI) signals are connected to the COM Express connector A-B from the AMD Fusion
Controller Hub. SPI BIOS is supported at the maximum level the FCH supports, 16 MBytes. Two BIOS disable straps, as
defined in the COM Express Rev 2.0 specification, allow the selection of either on-module SPI BIOS or carrier board
SPI or LPC BIOS.
The SPI interface can be used to connect two devices, one on the module and one on the carrier board, including
external BIOS flash memory. The implementation of this subsystem complies with the COM Express Rev 2.0
specification. Carrier Board SPI boot support is new with COM Express Rev 2.0. For additional implementation
information, refer to the
PICMG COM Express® Design Guide on the PICMG website.
5.9 LPC Bus Interface
The Low Pin Count (LPC) interface signals are connected to the LPC controller in the AMD Fusion Controller Hub. The
LPC low-speed interface can be used for peripheral circuits. For example, it can be used to interface to an external
super I/O controller to provide a legacy device. The implementation of this subsystem complies with the COM
Express
TM specification. For additional implementation information, refer to the PICMG COM Express® Design Guide on
the PICMG website.
Address (HEX) Device
0000 - 00FF IBM PC compatible devices (IRQ-Controller, Keyboard, RTC, etc.)
002E-002F Optional: Super I/O W83627
004e - 004f TPM
01F0 - 01F7 Fixed Disk
03C0 - 03CF VGA/EGA compatible registers
03F6 Fixed Disk
0400 - 043F SMBus
0480 - 04BF GPIO ICH
04D0 - 04D1 IRQ Configuration
08F0 - 08FF Optional
0900 - 091F Power Management
0A80 - 0A83 Reserved
0CF8 - 0CFF PCI Configuration
Table 8: LPC and Fixed I/O Addresses
DRAFT COPY FOR REVIEW ONLY
DRAFT COPY FOR REVIEW ONLY