Kontron MSM800SEL - Manual (Page 48)

MSM800SEV/SEL / Detailed System Description
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6.10.2 RTC (Real Time Clock)
An AT compatible date/time clock is located within the chipset. The device also contains a CMOS static RAM,
compatible with that in standard ATs. System configuration data is normally stored in the clock chip's CMOS RAM in a
manner consistent with the convention used in other AT compatible computers.
Connect an external lithium battery to X33 pin6 (or use the mounted battery). Be sure to use the correct polarity!
The battery-backed clock can be set by using the Kontron Compact Computers AG setup at boot-time.
Note: On all MSM800SEL/XEL boards – the battery must be connected externally! There is no battery assembled
onboard.
Attention: For systems that already have an onboard battery (MSM800SEV/BEV/XEV): if an external battery is to be
connected, then the onboard battery
must be removed first.
6.10.3 Watchdog
The watchdog timer detects a system crash and performs a hardware reset. After power up, the watchdog is always
disabled as the BIOS does not send strobes to the watchdog. In case the user wants to take advantage of the
watchdog, the application must produce a strobe at least every 800 ms. If no strobe occurs within the 800 ms, the
watchdog resets the system.
For more information, please refer to the BIOS/Driver/Software manual "GEODE_LX800-LX900" on the Product CD.
The watchdog feature is integrated in the INT15 function.
Some programming examples are available:
Product CD-Rom or customer download area: \TOOLS\DL-INT15_Tool\…
6.11 CMOS RAM Map
Systems based on the industry-standard specification include a battery backed Real Time Clock chip. This clock
contains at least 64Bytes of non-volatile RAM. The system BIOS uses this area to store information including system
configuration and initialization parameters, system diagnostics, and the time and date. This information remains
intact even when the system is powered down.
The BIOS supports 128Bytes of CMOS RAM. This information is accessible through I/O ports 70h and 71h. CMOS RAM
can be divided into several segments:
»
Locations 00h - 0Fh contain the real time clock (RTC) and status information
»
Locations 10h - 2Fh contain system configuration data
»
Locations 30h - 3Fh contain system BIOS-specific configuration data as well as chipset-specific information
»
Locations 40h - 7Fh contain chipset-specific information as well as power management configuration
parameters
The following table provides a summary of how these areas may be further divided.
Beginning Ending Checksum Description
00h 0Fh No RTC and Checksum
10h 2Dh Yes System Configuration
2Eh 2Fh No Checksum Value of 10h - 2Dh
30h 33h No Standard CMOS
34h 3Fh No Standard CMOS - SystemSoft Reserved
40h 5Bh Yes Extended CMOS - Chipset Specific
5Ch 5Dh No Checksum Value of 40h - 5Bh
5Eh 6Eh No Extended CMOS - Chipset Specific
6Fh 7Dh Yes Extended CMOS - Power Management
7Eh 7Fh No Checksum Value of 6Fh - 7Dh