Cirrus Logic CS6422 - Manual (Page 29)

CS6422
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3.9 Reset
A hardware reset, initiated by bringing RST low for
at least t
RSTL
and then high again, must be applied
after initial power-on.
When RST is held low, the various internal blocks
of the CS6422 are powered down. When RST is
brought high, the oscillator is enabled and approx-
imately 4 ms later, all digital clocks begin operat-
ing. The ADCs and DACs are calibrated and all
internal digital initializations occur.
The CS6422 supports two reset modes, cold reset
and warm reset. The reset mode is selected by
completing a write of a specified value to the MCR
within T
wRST
of the rising edge of RST. If no
writes to the MCR occur within T
cRST
, then a cold
reset is initiated by default at the end of the T
cRST
time period.
The value written to the MCR determines the be-
havior of the CS6422:
1) a value of ‘0x0000’ will initiate a cold reset
when the reset timer expires. This is the default
behavior of the device.
2) a value of ‘0x0006’ will initiate a warm reset
when the reset timer expires.
3) a value of ‘0x8000’ will initiate a cold reset im-
mediately, bypassing the reset timer.
4) a value of ‘0x8006’ will initiate a warm reset
immediately, bypassing the reset timer.
Values (#2) through (#4) above are interpreted as
legitimate register writes (to register 0 for (#3) and
to register 3 for (#2) and (#4)) of the CS6422.
Therefore, it is important to follow the first register
write with another write containing the proper set-
tings for register 0 or register 3.
3.9.1 Cold Reset
Cold reset initializes all the components of the
CS6422. The ADCs and DACs are reset, the echo
canceller memories and registers are cleared, and
the default settings of the MCR are restored.
3.9.2 Warm Reset
Warm reset is like cold reset except that the echo
canceller coefficients and certain key variables are
not cleared, but instead keep their pre-reset value.
This gives the CS6422 a headstart in adapting to its
environment if the echo environment is relatively
stable, assuming a cold reset occurred at least once
since power up.
3.9.3 Reset Timer
Another special reset option is to exit the T
wRST
re-
set timer before the T
wRST
has elapsed. This timer
halts device operation until the analog bias voltages
have had time to settle. The early-exit option
should be used only in applications in which the
T
wRST
start-up delay is unacceptable.
3.10 Clocking
The clock for the converters and DSP is provided
via the clocking pins, CLKI (pin 14) and CLKO
(pin 13). A 20.480 MHz parallel resonant crystal
placed between these two pins and loaded with
22 pF capacitors will allow the on-chip oscillator to
provide this system clock. Alternatively, the CLKI
pin may be driven by a CMOS level clock signal.
The clock may vary from 20.480 MHz by up to
10%, however, this will change the sampling rate
of the converters and echo canceller, which will af-
fect the bandwidth of the analog signals and the du-
ration of echo that the echo canceller can
accommodate. CLKO is not connected when CLKI
is driven by the CMOS signal.
CS6422
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