Cirrus Logic AN299 - Manual (Page 6)

6 AN299REV1
AN299
16 (CS5531/3) or 24 (CS5532/4) bits and placed in the output register. At reset the value in all of the offset registers
is zero (0x00000000) and the gain correction registers contain a gain multiplier of one (0x01000000). If the offset
and gain corrections are not required by an application, as is often the case in ratiometric applications, the gain cal-
ibration register can be used to change the full-scale input span of the ADC. For example, if the channel setup is
programmed for a gain of 64x in unipolar mode, the full-scale input span with a 2.5 V DC reference (VRS = 1) or 5 V
DC reference (VRS = 0) would be 39.0625 mV. However, if it is desired to have the full-scale range be 10 mV, this
could be achieved by writing a value of 3.90625 (0x03E80000) into the gain calibration register for that channel.
Since the internal resolution of the filter's output is several bits greater than the output word resolution, multiplying
by 3.90625 results in almost two bits of that internal resolution being utilized in the output that would have otherwise
been truncated. This in itself does not improve the noise-free resolution of the output, but with adequate software
averaging of this output, additional noise-free bits are possible as long as the noise distribution is Gaussian. It should
be pointed out that if this method is used, the offset register should be zero. Otherwise an offset calibration should
be performed after the gain register is written because the offset value will also be multiplied by the gain register
value.
6. DC MEASUREMENT AVERAGING
The above section referred to averaging the ADC readings in software in order to obtain additional noise-free bits
of resolution. In DC measurement, where the input seldom changes, this can be a simple average. Otherwise a run-
ning average or a more adaptive, weighted average that detects changes in the DC input above a certain threshold
can be used. Which method is used and what sample rate is used will depend on the system requirements for the
DC reading. How much latency can be tolerated between an input change and the completely settled result needs
to be determined before an averaging algorithm is chosen. The purpose of this explanation is simply to suggest a
few methods that could be implemented, especially when noise-free resolution is the main concern.
Before a software averaging algorithm is chosen, the sample rate for the converter should be selected. For measur-
ing a steady-state DC input, the advantages of using a low sample rate such as 7.5 Sps should be noted. To remove
as much of the noise as possible, lower sample rates take better advantage of the on-chip digital filter. However,
this conversion rate is based on the CS553x continuous conversion mode where complete settling only occurs after
four conversions. If the input multiplexer is used, single conversion mode is recommended because each conversion
is fully settled (in essence the part converts the input four times before giving an output word). The slowest output
rate in this case is approximately 1.8 Sps. Therefore in many applications where the inputs are being multiplexed it
may be desirable to use a higher conversion rate and average each input in software to remove some of the noise.
There is an advantage in using conversion rates of 60 Sps (50 Sps when FRS = 1) or lower because power line
frequency rejection is excellent at these rates due to a notch in the sinc3 filter at this frequency.
Once the conversion rate is determined, a software algorithm for averaging the readings for each channel to remove
more noise may be useful. A simple running average of eight is where only the last eight conversions are added
then divided by eight giving each conversion equal weight. This average fully settles in eight conversions since all
conversion results before the last eight are discarded. Simple exponential averaging is defined as each new read-
ing being a fractional part of the averaged result. For example, if the new reading is multiplied by 0.125 and then
added to the previous average multiplied by 0.875 then the new reading becomes 1/8 of the average. In this algo-
rithm the most-recent value has the highest weight with older conversions diminishing in weight exponentially. How-
ever, this exponential averaging has the highest latency because it takes many conversions for a single reading to
be completely flushed from the average, especially when a step change occurs on the input. In fact, a full-scale
change on a 24-bit converter would take 83 conversions for the average to settle to 16 bits of accuracy. Another
algorithm is the adaptive exponential average. In this case, the weight of the new ADC reading depends on the
difference between it and the previous average. Here a threshold needs to be determined that indicates that a step
change has occurred on the input. This threshold should be above normal peak-to-peak system noise in order that
noise below the threshold can be averaged out by the normal exponential average. However, if the new reading is
beyond the normal peak-to-peak noise threshold, the new reading supersedes the average so that the step is made
in a single conversion. This algorithm has numerous possibilities if multiple thresholds are specified with each step