Cirrus Logic CS5351 - Manual (Page 15)

DS565F2 15
CS5351
3. TYPICAL CONNECTION DIAGRAM
FILT+
AINL
V D
0.01 μF
A/D CONVERTER
SCLK
CS5351
M/S
MCLK
AINR
47 μF
+
RST
VA V L
+5V
1 μF
+5V to 2.5V
5.1 Ω 1 μF
+
+ +
SDOUT
GND
I 2 S/LJ
LRCK
GND
Power Down
and Mode
Settings
Audio Data
Processor
Timing Logic
and Clock
0.01 μF
HPF
M0
M1
REFGND
MDIV
+5 V to 3.3 V
1 μF
Analog
Input
Buffer
(Figure 24)
OVFL
VL
10 k Ω
* Resistor may only be used
if VD is derived from VA. If
used, do not drive any other
logic from VD
*
0.01 μF
0.01 μF 0.01 μF
VQ1
VQ3
VQ2
Figure 22. Typical Connection Diagram