Cirrus Logic CDB5346 - Manual (Page 8)

8 DS861DB1
CDB5346
3.3.2 12.288MHz, CS8406 Master - ADC Ch 1 In to SPDIF Out
Using the pre-configured script file named “12.288MHz _CS8406 Master_- ADC Ch 1 In to SPDIF
Out.fgs”, an analog input signal applied to channel 1 of the CS5346 input multiplexer will be digitized by
the ADC and transmitted in S/PDIF format by the CS8406 in Master Mode. No signal will be output
through the active output filter and RCA jacks.
The CS2000-CP is operated in frequency synthesizer mode to generate the 12.288 MHz master clock.
The CS8406 is the sub-clock master to the CS5346 and the PCM I/O header.
3.3.3 12.288MHz, J10 Master - ADC Ch 1 In to SPDIF Out
Using the pre-configured script file named “12.288MHz _J10 Master_- ADC Ch 1 In to SPDIF Out.fgs”, an
analog input signal applied to channel 1 of the CS5346 input multiplexer will be digitized by the ADC and
transmitted in S/PDIF format by the CS8406. No signal will be output through the active output filter and
RCA jacks.
The CS2000-CP is operated in frequency synthesizer mode to generate the 12.288 MHz master clock.
The PCM I/O header is the sub-clock master to the CS5346 and the CS8406.