Cirrus Logic CDB5346 - Manual (Page 5)

DS861DB1 5
CDB5346
2. SYSTEM CLOCKS AND DATA
The CDB5346 implements comprehensive clock routing capabilities. Configuration of the clock routing can be easily
achieved using the controls within the Board Controls group box on the CDB5346 Controls tab in the GUI software
application.
2.1 Clock Routing
The master clock signal (MCLK) is always sourced from the CS2000-CP (U18). The CS2000-CP can be
configured to either synthesize a clock from the crystal (Y1) or to be phase locked looped to either the MCLK
or LRCK input from the PCM I/O header (J21).
The sub-clock signals (SCLK and LRCK) may be sourced from the CS5346 in master mode, the CS8406 in
master mode, or the PCM I/O header.
Clock routing configuration is achieved using the controls within the Board Controls group box on the
CDB5346 Controls tab in the GUI software application.
2.2 Data Routing
The serial data output of the CS5346 is routed to both the CS8406 S/PDIF transmitter and the PCM I/O
header. No user configuration of the serial data routing is required.