Cirrus Logic AN285 - Manual (Page 6)

6 AN285REV1
AN285
6. SYSTEM CLOCKING
6.1 CS5333 Clock Options
The CS5333 supports an MCLK/LRCK ratio of 256x, 384x, 512x, and 768x in Base-Rate Mode, and 128x,
192x, 256x, and 384x in High-Rate Mode. However, in Master Mode, MCLK/LRCK ratios of 384x, 768x, and
192x are not accessible. Table 3 shows the available MCLK/LRCK ratios in each mode of operation for the
CS5333.
Furthermore, the CS5333 supports sample rates from 2 to 50 kHz in Base-Rate Mode and 50 to 100 kHz in
High-Rate Mode.
6.2 CS5343/4 Clock Options
Table 4 shows the MCLK/LRCK ratios the CS5343/4 can support in the various modes of operation.
In Slave Mode, the CS5343/4 supports MCLK/LRCK ratios of 128x, 192x, 256x and 384x when running in
either Single-Speed or Double-Speed. Also in Slave Mode, the CS5343/4 sample-rate can range continu-
ously from 4 to 54 kHz in Single-Speed Mode or 86 - 108 kHz in Double-Speed Mode.
In Master Mode, the CS5343/4 defaults to an MCLK/LRCK ratio of 256x due to the presence of a 100 k
Ω
internal pull-down resistor between the SCLK pin and GND. An external 10 k Ω pull-up resistor from the
SCLK pin to VA will configure the device to output an LRCK corresponding to an MCLK/LRCK ratio of 384x,
depending on MCLK frequency. With the correct MCLK frequency and clock divider settings, the CS5343/4
sample-rate can range continuously from 4 to 54 kHz in Single-Speed Mode or 50 to 108 kHz in Double-
Speed Mode.
Device Master/Slave Speed Supported MCLK/LRCK Ratio
CS5333
Master
Base-Rate 256x
High-Rate 128x
Slave
Base-Rate 256x, 384x, 512x, 768x, 1024x
High-Rate 128x, 192x, 256x, 384x
Table 3. CS5333 Supported MCLK/LRCK Ratios
Device Master/Slave Speed Supported MCLK/LRCK Ratio
CS5343/4
Master
Single-Speed 256x, 384x
Double-Speed 256x, 384x
Slave
Single-Speed 128x, 192x, 256x, 384x
Double-Speed 128x, 192x, 256x, 384x
Table 4. CS5343/4 Supported MCLK/LRCK Ratios