Cirrus Logic AN285 - Manual (Page 5)

AN285REV1 5
AN285
5. MODE SELECTIONS: MASTER/SLAVE & SPEED MODES
5.1 CS5333 Mode Selections
5.1.1 Master/Slave Mode Selection
The CS5333 operates in either Master Mode or Slave Mode depending on the pull-up or pull-down resistor
on the SDATA pin. A 47 k
Ω pull-up resistor between SDATA and VL selects Master Mode while a 47 kΩ
resistor between SDATA and GND will select Slave Mode.
5.1.2 Speed Mode Selection
The CS5333 features a DIV pin which allows the user to configure speed in Master Mode. In Master Mode,
the user can tie DIV high (VL) to select Base-Rate mode or low (GND) to select High-Rate mode. In Slave
Mode, the CS5333 auto-detects speed mode and the DIV pin enables an MCLK divide-by-two function
when set high.
5.2 CS5343/4 Mode Selections
5.2.1 Master/Slave Mode Selection
The CS5343/4 enters Master Mode when a 10 k
Ω pull-up resistor is present between SDOUT and the VA
supply. Conversely, Slave Mode is selected via a pull-down resistor between SDOUT and GND.
5.2.2 Speed Mode Selection
Similar to the CS5333, the CS5343/4 auto-detects Speed Mode when operating as a slave. In Master
Mode, an internal 100 k
Ω pull-down resistor on the LRCK pin will set the device for Single-Speed Mode
by default. An external 10 k
Ω pull-up resistor from the LRCK pin to VA will over-ride the default setting
and select for Double-Speed Mode.
Unlike the CS5333, the CS5343/4 features additional auto-detect circuitry to automatically enable an
MCLK divide-by-two function.