Figure 5. external serial mode input timing, Figure 6. internal serial mode input timing, Figure 7. internal serial clock generation – Cirrus Logic CS4339 User Manual
Page 11: Figure 5, External serial mode input timing, Figure 6, Internal serial mode input timing, Figure 7, Internal serial clock generation
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CS4334/5/8/9
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 5. External Serial Mode Input Timing
SDATA
*INTERNAL SCLK
LRCK
sclkw
t
sdlrs
t
sdh
t
sclkr
t
Figure 6. Internal Serial Mode Input Timing
The SCLK pulses shown are internal to the CS4334/5/8/9.
SDATA
LRCK
MCLK
*INTERNAL SCLK
1
N
2
N
Figure 7. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4334/5/8/9.
N equals MCLK divided by SCLK