Cirrus Logic CDB4207 - Manual (Page 4)

CDB4207
4 DS880DB1
stereo full-differential outputs are available at J66 and J53. For lineout 2, the single-ended or full-differential
output option is selected using J54 and J55. The stereo single-ended output is available at J69. The stereo
full-differential outputs are available at J64 and J65.
The headphone output jack presence detect signal is triggered by inserting a plug into J48 or shunting J49.
The lineout 1 jack presence detect signal is triggered by inserting a plug into J70 or shunting J67. Since the
CS4207 can only support four jack detect signals on the SENSE_A pin (MIC input, line input, headphone
output, and lineout 1), the lineout 2 jack presence detect signal uses the CS4207’s GPIO pins. The detect
signal can be connected to GPIO2 or GPIO3 using J35. The signal is triggered by inserting a plug into J69.
See Figure 4 on page 13 for the analog output circuit schematic and Section 3 on page 7 for the analog
output connections and jumper selections. There is no on-board signal attenuation; see CS4207 datasheet
for full-scale output amplitudes.
1.4 Digital Microphone Inputs
The two stereo digital microphone inputs use 4-pin headers for connection to the CS4207. Digital MIC 1
uses headers J29 and J30 while digital MIC 2 uses headers J31 and J32. Pin 1 of each header is connected
to DMIC_SCL, the digital microphone clock signal from the CS4207. Pin 2 of each header is the data input
signal to the CS4207. The data signals are multiplexed for each header pair (J29/J30 and J31/J32) to sup-
port stereo signals. Pin 3 of each header is fixed to a 3.3 V supply from an on-board regulator. Pin 4 of each
header is fixed to ground.
See Figure 5 on page 14 for the digital microphone circuit schematic and Section 3 on page 7 for the digital
microphone connections.
1.5 S/PDIF I/O
All S/PDIF I/O signals on the CDB4207 use optical connectors. The S/PDIF input signal to the CS4207 is
supplied at J39. The S/PDIF output 1 signal from the CS4207 is available at J26. The S/PDIF output 2 signal
from the CS4207 is available at J71. Since the S/PDIF output 2 signal from the CS4207 uses a multi-pur-
pose pin, it can be disconnected from J71 by unshunting J16.
See Figure 5 on page 14 for the S/PDIF I/O circuit schematic and Section 3 on page 7 for the S/PDIF I/O
connections and jumper selections.
1.6 GPIO Header
The CS4207’s four GPIO pins are available at header J34. The GPIO signals are located in the middle col-
umn of the header. A 10 k
Ω pull-down or pull-up resistor can be applied to each GPIO signal by shunting
the middle column to column 1 or 3, respectively.
See Figure 5 on page 14 for the GPIO header circuit schematic and Section 3 on page 7 for the GPIO head-
er connections and jumper selections.
1.7 HD Audio Bus Headers
The CDB4207 has duplicate HD Audio Bus headers for connection to a PC (J1 and J9). These headers al-
low for easy daisy chaining between CDB4207s for systems with multiple HD Audio CODECs. See
Table 1
for header pinout. The headers are keyed for a standard 16-pin ribbon cable. The header cable should only
be connected or disconnected while the PC power is turned off. An alternate HD Audio Bus header for the
digital I/O signals only is available at J20. The CS4207 will be connected to the serial digital input (SDI) line
of the HD Audio Controller selected by header J21. See
Figure 5 on page 14 for the HD Audio Bus header
circuit schematic and Section 3 on page 7 for the HD Audio Bus header connections and jumper selections.