Cirrus Logic CS2300-CP - Manual (Page 3)

CS2300-CP
DS843F2 3
8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 28
8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 28
8.6.3 Enable Device Configuration Registers 3 (EnDevCfg3) ........................................................ 28
8.7 Function Configuration 2 (Address 17h) ........................................................................................ 29
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 29
8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 29
8.8 Function Configuration 3 (Address 1Eh) ........................................................................................ 29
8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 29
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 30
9.1 High Resolution 12.20 Format ....................................................................................................... 30
9.2 High Multiplication 20.12 Format ................................................................................................... 30
10. PACKAGE DIMENSIONS .................................................................................................................. 31
THERMAL CHARACTERISTICS ......................................................................................................... 31
11. ORDERING INFORMATION .............................................................................................................. 32
12. REFERENCES .................................................................................................................................... 32
13. REVISION HISTORY .......................................................................................................................... 32
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 6
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 9
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 9
Figure 4. CLK_IN Random Jitter Rejection and Tolerance ......................................................................... 9
Figure 5. Control Port Timing - I²C Format ................................................................................................ 10
Figure 6. Control Port Timing - SPI Format (Write Only) .......................................................................... 11
Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 12
Figure 8. Hybrid Analog-Digital PLL .......................................................................................................... 13
Figure 9. External Component Requirements for LCO ............................................................................. 14
Figure 10. CLK_IN removed for > 2
23
LCO cycles ................................................................................... 15
Figure 11. CLK_IN removed for < 2
23
LCO cycles but > t
CS ....................................................................................... 15
Figure 12. CLK_IN removed for < t
CS .................................................................................................................................. 16
Figure 13. Low bandwidth and new clock domain .................................................................................... 17
Figure 14. High bandwidth with CLK_IN domain re-use ........................................................................... 17
Figure 15. Ratio Feature Summary ........................................................................................................... 19
Figure 16. PLL Clock Output Options ....................................................................................................... 20
Figure 17. Auxiliary Output Selection ........................................................................................................ 20
Figure 18. Control Port Timing in SPI Mode ............................................................................................. 22
Figure 19. Control Port Timing, I²C Write .................................................................................................. 23
Figure 20. Control Port Timing, I²C Aborted Write + Read ....................................................................... 23
LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 18
Table 2. Example 12.20 R-Values ............................................................................................................ 30
Table 3. Example 20.12 R-Values ............................................................................................................ 30