Cirrus Logic CS2300-CP User Manual
Cs2300-cp, Fractional-n clock multiplier with internal lco, Features

Copyright
Cirrus Logic, Inc. 2010
(All Rights Reserved)
Fractional-N Clock Multiplier with Internal LCO
Features
Clock Multiplier / Jitter Reduction
–
Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to 30
MHz Clock Source
Internal LC Oscillator for Timing Reference
Highly Accurate PLL Multiplication Factor
–
Maximum Error less than 1 PPM in High-
Resolution Mode
I²C™ / SPI™ Control Port
Configurable Auxiliary Output
Minimal Board Space Required
–
No External Analog Loop-filter
Components
General Description
The CS2300-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2300-CP is based on a hybrid ana-
log-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an exter-
nal noisy synchronization clock at frequencies as low
as 50 Hz. The CS2300-CP supports both I²C and SPI
for full software control.
The CS2300-CP is available in a 10-pin MSOP pack-
age in Commercial (-10°C to +70°C) and Automotive
(-40°C to +85°C) grades. Customer development kits
are also available for device evaluation. Please see
“Ordering Information” on page 31
for complete details.
I²C / SPI
Auxiliary
Output
6 to 75 MHz
PLL Output
Frequency Reference
3.3 V
I²C/SPI
Software Control
Fractional-N
Frequency Synthesizer
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
N
PLL Output
Lock Indicator
50 Hz to 30 MHz
Frequency
Reference
LCO
MAY '10
DS843F2
CS2300-CP
Document Outline
- 1. Pin Description
- 2. Typical Connection Diagram
- 3. Characteristics and Specifications
- 4. Architecture Overview
- 5. Applications
- 6. SPI / I·C Control Port
- 7. Register Quick Reference
- 8. Register Descriptions
- 8.1 Device I.D. and Revision (Address 01h)
- 8.2 Device Control (Address 02h)
- 8.3 Device Configuration 1 (Address 03h)
- 8.4 Global Configuration (Address 05h)
- 8.5 Ratio (Address 06h - 09h)
- 8.6 Function Configuration 1 (Address 16h)
- 8.7 Function Configuration 2 (Address 17h)
- 8.8 Function Configuration 3 (Address 1Eh)
- 9. Calculating the User Defined Ratio
- 10. Package Dimensions
- 11. Ordering Information
- 12. References
- 13. Revision History