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2 aux pll lock output configuration (auxlockcfg), 3 reference clock input divider (refclkdiv[1:0]), 8 function configuration 2 (address 17h) – Cirrus Logic CS2000-CP User Manual

Page 32: 1 enable pll clock output on unlock (clkoutunl), 2 low-frequency ratio configuration (lfratiocfg), P 32, Aux pll lock output config, Cs2000-cp

2 aux pll lock output configuration (auxlockcfg), 3 reference clock input divider (refclkdiv[1:0]), 8 function configuration 2 (address 17h) | 1 enable pll clock output on unlock (clkoutunl), 2 low-frequency ratio configuration (lfratiocfg), P 32, Aux pll lock output config, Cs2000-cp | Cirrus Logic CS2000-CP User Manual | Page 32 / 38 2 aux pll lock output configuration (auxlockcfg), 3 reference clock input divider (refclkdiv[1:0]), 8 function configuration 2 (address 17h) | 1 enable pll clock output on unlock (clkoutunl), 2 low-frequency ratio configuration (lfratiocfg), P 32, Aux pll lock output config, Cs2000-cp | Cirrus Logic CS2000-CP User Manual | Page 32 / 38
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