Cirrus Logic AN312 - Manual (Page 6)

6 AN312REV2
AN312
Figure 9. 0x01 Mode Typical Connection - Synchronization of All Nodes
Note: All nodes should be on house synch.
Figure 10. Mode 0x01 Clock Circuit Used with CM-1 Modules
CobraNet Interface
(External Word Clock
Mode)
FS1
SCLK
REFCLK
CobraNet Interface
(External Word Clock
Mode)
SCLK
REFCLK
CobraNet Interface
(External Word Clock
Mode)
FS1
SCLK
REFCLK
48 kHz House Sync
MCLK_OUT MCLK_OUT MCLK_OUT
FS1
Beat Received
VCXO
24.576MHz
+/- 100 PPM
DAC
MCLK_IN
MCLK_SEL
REFCLK_Enable
REFCLK_Polarity
REFCLK
Edge
Detect
MCLK
MUX
Beat
MUX
Phase
Detector
Sample
Phase
Counter
RST
Loop
Filter
control
Clock
Out
MCLK_OUT (master)
FS1 (word)
SCK (bit)
Audio
Clock
Generator
Clock Config
Signal
Path
Control
Path
Hardware FPGA Software Active
Signal
Path