PNI RM3000 Evaluation Board - Manual (Page 11)

RM3000 Evaluation Board User Manual – June 2011 Page 11 of 19
Note: If a new command sequence is started before the previous measurement has
completed (before DRDY goes HIGH), the previous command will be overwritten. This will
also stop the measurement cycle. If you try to send a new command during the readout
phase, after DRDY goes HIGH, the command will be ignored until all 16 bits have been
clocked our or the CLEAR pin is set HIGH (then LOW again).
CLEAR (Clear Command Register)
To initiate a clear command in Legacy Mode, the CLEAR pin must be toggled LOW-
HIGH-LOW. CLEAR is usually LOW. CLEAR will reset the DRDY pin to LOW.
CLEAR can be used to stop any sensor measurement in progress. CLEAR has no
effect on the SPI register state.
Note: The CLEAR pin is simi lar to the RESET pin on PNI’s legacy ASIC. However in
Standard Mode the 3D MagIC automatically resets the DRDY line, so it is not necessary to
use the CLEAR pin when operating in Standard Mode.
Vdd (Supply Voltage)
The recommend supply voltage, Vdd, and associated ripple are defined in Table 3-2,
and the maximum voltage is given in Table 3-1.
GND (Ground Pins)
The two ground pins may be tied to a clean common ground plane or they may have
their own ground planes. The pins should be within 0.1 V of each other.
4.3 SPI Interface Operation
When implementing an SPI port, whether a dedicated hardware peripheral port or a software-
implemented port using general purpose I/O (also known as Bit-Banging), the timing
parameters (defined below in Figure 4-1 and specified in Table 4-2) must be met to ensure
reliable communications. The SPI clock (SCLK) should run at 1 MHz or less. Generally
data is considered valid while SCLK is HIGH, and data is in transition when SCLK is LOW.
The clock polarity used with the 3D MagIC is zero (CPOL=0). Data is present on MISO or
should be presented on MOSI before the first low to high clock transition (CPHA = 0).