Atec Tektronix-ST2400A - Manual (Page 5)

page 5
ST2400A
Transmitter
Specifications
Continued PAYLOAD GENERATION
2.488 Gbit/s signal framing and multiplex-
ing format to meet ITU-T G.707 and
Bellcore GR-253-CORE.
Output Timing –
INT mode: Generated from internal
2.488 Gbit/s ±20 ppm clock or external
1.544 Mbit/s, 2.048 MHz, or 2.048
Mbit/s ref clock.
THRU mode: Generated from clock
recovered from 2.488 Gbit/s input.
EXT mode: Generated from clock, recov-
ered from 155/622 Mbit/s add input.
OUTPUT SIGNAL STRUCTURE
1. Active THRU (Through) Mode
Regenerated with recomputed B1, B2 but
otherwise unaltered or with user-modified
overhead, added defects, or added errors
from the received 2.488 Gbit/s input signal
using the recovered clock. Jitter transfer
from 2.488 Gbit/s input to output is filtered
by a 1 MHz (nominal) bandwidth PLL
(typical 0.3 dB jitter transfer).
2. EXT (Terminal) Mode
155 or 622 Mbit/s tributary signals are
added from an external SDH or SONET test
set. 2.488 Gbit/s signal is generated using
clock recovered from the add input. Tribu-
tary signals added into any 1 of 16
(155 Mbit/s) or any 1 of 4 (622 Mbit/s) pay-
load locations or duplicated to fill all pay-
load locations. Unused payload locations
are VC-4 structured STM-1 (SDH mode)
STS-3C structured STS-3, or 3 x STS-1
(SONET mode) structured with unequipped
path overhead (J1=0, C2=0, correct B3,
remainder of path overhead =0). The
remainder of the channel payload is bulk-
filled with user-selected test pattern (all
Zeros, ITU-T 0.181 2
23 -1 PRBS, or 2 23 -1
PRBS). In "all" mode, the tributary overhead
is copied to fill all the 2.488 Gbit/s over-
head; in "single" mode, one copy is made for
the selected location and all other locations
are filled with "unequipped" channel over-
head and user-selected test patterns (all
Zeros, ITU-T 0.181 2
23 -1 PRBS, or
2 23 -1 PRBS).
3. INT (Standalone) Mode
2.488 Gbit/s signal is VC-4 structured STM-
1 (SDH), STS-3C structured STS-3, or 3 x
STS-1 (SONET) structured and filled with
test patterns as in External Mode. Default
overhead: A1 and A2 are set to F6H and
28H, respectively; J0 byte is set to 1; 15 Z0
bytes and 32 National Use bytes (formerly
C1 bytes) are numbered from 2 to 48 (deci-
mal); H1 is set to 6AH and H2 is set to 0AH
for valid STS/STM pointers.
B1 contains computed B1 BIP and B2 con-
tains computed B2 BIP; all other overhead
set to 00H.
J1 and C2 in path overhead set to 0. B3 BIP
set to correctly computed parity. All other
path overhead set to 00.
OVERHEAD EDITING
Overhead bytes in STS-1, column 1 can be
independently set as hex values in the range
00 to FF.
Settable bytes: J0, E1, F1, D1-D3, K1, K2,
D4-D12, S1, M1, E2.
Following bytes may not be directly edited:
A1, A2, B1, B2, B3, H1-H3.
Clear-text coding and dedicated menus for
S1 (Synchronization Status Byte) and K1/K2
(MSP – Multiplex Section Protection/APS
– Automatic Protection Switching).
Active THRU (Through) Mode: Overhead
bytes are regenerated from the 2.488 Gbit/s
input and can be selectively overwritten.
B1 and B2 are recalculated prior to
transmission.
EXT (Terminal) Mode: All bytes except for
B1 are inserted from the tributary into one
or all envelopes. Settable bytes can be
selectively overwritten. B1 and B2 are recal-
culated prior to transmission.
INT (Standalone) Mode: All bytes are gener-
ated internally. Settable bytes can be selec-
tively overwritten.
DEFECT/ALARM GENERATION – LOS, LOF, MS-AIS/AIS-L,
MS-RDI/RDI-L
Multiple defects and alarms can be set for
simulation of real network conditions.
Duration Control –
LOS: 1 to 127 µs (1µs resolution).
LOF, MS-AIS/AIS-L, MS-RDI/ RDI-L: 1 to
127 frames (1 frame resolution).
All: 0.1 to 9.9 s (0.1 s resolution).
Continuous or off.
Interval Control: Repeat On/Off.
Injection time: 0.1 to 9.9 s.
Idle time: 1.0 to 30 s.
Resolution (all): 0.1 s.
ERROR GENERATION B1, MS-REI/REI-L, BIT
Error Control –
B1 (BIP-8): Single error or continuous error
rate, 2.5E-5 to 0.1E-9.
B2 (BIP-24): Single error in one or all
channels or continuous error rate, 1.0E-3
to 0.1E-9.
B3: Single error in one or all channels or
continuous error rate 1.0E-3 to 0.1E-9.
MS-REI/ REI-L: M1 byte is overwritten. 0 to
255 errors per frame inserted in a single
frame, continuously, or for a duration of 0.1
to 9.9 s; Resolution, 0.1 s.
Bit errors in selected STM-1/STS-1 tributary
or across 2.488 Gbit/s frame.
Single error or continuous error rates,
1.0E-3 to 0.1E-9.
Interval Control: Repeat On/Off.
Injection time: 0.1 to 9.9 s.
Idle time: 1.0 to 30 s.
Resolution (all) : 0.1 s.
Other Interfaces –
Clock Sync Output: 1/8 rate, AC-coupled,
300 mV
p-p
(minimum), SMA connector.
Frame Sync Output: 50 Ω , ECL, 25.8 ns
pulse width, BNC connector.
Event Trigger Output: 50
Ω
, TTL, 25.8 ns
pulse width, BNC connector.
Pulse transmitted for each alarm, error, or
overhead event (selectable).