Atec Anritsu-MP1763B - Manual

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DIGITAL TRANSMISSION MEASURING INSTRUMENTS
GPIB
9
The MP1763B is used in combination with the MP1764A Error Detector.
The amplitude of the clock and data signals can be varied from 0.25
to 2 Vp-p while the offset can be adjusted to within ±2 V so that the
amplitude and the offset margin can be measured. The clock has a
variable delay function so that time-dependent characteristics or
phase margins of the input clock and data can be measured. An M
series pseudorandom pattern representative of actual conditions or
a programmable pattern can be selected as cell data.
In addition, a 3.5 inch floppy disk drive is built in for storing preset
data, enabling rapid measurements to be performed by simply press-
ing a key. A GPIB function is provided, enabling automatic or remote
measurement via an external controller.
The MP1763B is a pulse pattern generator ideal for research and
development of high-speed logic, ICs, and digital systems.
Features
•
High quality waveform
•
Low FM/PM-noise clock generator
•
8 Mbit programmable pattern corresponding to six frames of STM-
64/STS-192
•
Generates PRBS patterns with bit length from 2 7 –1 to 2 31 –1 bits
•
Complementary outputs of both data and clock
•
The amplitudes and offsets of all 8 data outputs that have 1/8
speed of fundamental clock signal can be set
PULSE PATTERN GENERATOR
MP1763B
12.5 GHz
Specifications
Operation Internal clock 0.05 to 12.5 GHz (option)
frequency
External clock 0.05 to 12.5 GHz
Input level 0.4 to 2.5 Vp-p
External Square wave with rise/fall time of less than 1 ns, duty factor 50% (0.05 to 0.5 GHz); Sinusoidal wave or square
clock
Input waveform
wave with rise/fall time of less than 1 ns, duty factor 50% (>0.5 GHz)
Input connector APC-3.5
Frequency range 0.05 to 12.5 GHz (option)
Frequency setting resolution 1 kHz, 1 MHz
Internal Stability ±1 ppm
clock
SSB phase noise (at 10 kHz
–85 dBc/Hz (0.05 to 4 GHz), –80 dBc/Hz (4 to 8 GHz), –75 dBc/Hz (8 to 10 GHz), –70 dBc/Hz (10 to 12.5 GHz)
offset, 1 Hz bandwidth)
Reference signal 10 MHz (internal/external, selectable)
Pseudorandom binary
Pattern: 2 n – 1 (n: 7, 9, 11, 15, 20, 23, 31)
sequence pattern (PRBS)
Mark ratio: 1/2, 1/4, 1/8, 0/8 (1/2, 3/4, 7/8, 8/8 are possible with logic inversion)
Number of AND bit shifts when setting mark ratio: 1, 3 bit (selectable by using DIP switch on rear panel)
Data pattern* 1 Data length: 2 to 8388608 bits; Pattern reset/preset: ALL/PAGE selectable
Pattern Logic inversion Provided
Alternate pattern A/B pattern data length: 128 to 4194304 (128 bit steps); Loop time: A, B pattern (1 to 127, 1 steps)
Zero substitution pattern Zero bit length: 1 to (pattern length – 1) bits; Pattern: 2 n (n: 7, 9, 11, 15)
Error rate: 10 –n (n: 4, 5, 6, 7, 8, 9), and single error
Error addition
Addition position (selectable with rear panel DIP switch): Possible to insert into any 1 CH of 32 CH
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