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Data sheet, High sensitivity cmos hall-effect latch ah921, Test circuit and test conditions (continued) – Diodes AH921 User Manual

Page 8

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Data Sheet

HIGH SENSITIVITY CMOS HALL-EFFECT LATCH AH921

Jul. 2011 Rev. 1. 2 BCD Semiconductor Manufacturing Limited

8

Test Circuit and Test Conditions (Continued)





Figure 8. Test Condition of AH921 (Supply Current)




Note 4: Output initial status is low when powering on.
Note 5: The supply current I

CC

represents the average supply current. The output is open during measurement.

Note 6: The device is put under the magnetic field: B

RP.









Figure 9. Test Condition of AH921 (Output Saturation Voltage)




Note 7: The output saturation voltage V

SAT

is measured at V

CC

=3.5V and V

CC

=24V.

Note 8: The device is put under the magnetic field: B>B

OP.



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