Diodes AP3586A/B/C - Manual (Page 14)

Data sheet
Single Phase Synchronous Buck PWM Controller AP3586A/B/C
Mar. 2012 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
14
Function Description (Continued)
oscillator are turned off and UGATE and LGATE are
driven low, turning off both MOSFETs. When the
junction cools to the required level (140°C
nominal), the PWM initiates soft start as during a
normal power-up cycle.
Output Voltage Selection
The output voltage can be programmed to any level
between the 0.6V internal reference (0.8V for
AP3586B/C) to the 82% of V
IN
supply. The lower
limitation of output voltage is caused by the internal
reference. The upper limitation of the output voltage
is caused by the maximum available duty cycle
(82%). This is to leave enough time for over-current
detection. Output voltage out of this range is not
allowed.
A voltage divider sets the output voltage (Refer to the
typical application circuit). In real applications,
choose R1 in 100Ω to 10kΩ range and choose
appropriate R2 according to the desired output
voltage.
AP3586A
AP3586B/C
PCB Layout Considerations
High speed switching and relatively large peak
currents in a synchronous-rectified buck converter
make the PCB layout a very important part of design.
Switching current from one power device to another
can generate voltage spikes across the impedances of
the interconnecting bond wires and circuit traces. The
voltage spikes can degrade efficiency and radiate
noise, that results in over-voltage stress on devices.
Careful component placement layout a printed circuit
design can minimize the voltage spikes induced in the
converter.
Follow the below layout guidelines for optimal
performance of AP3586A/B/C.
1) The turn-off transition of the upper MOSFET
prior to turn-off, the upper MOSFET was
carrying the full load current. During turn-off,
current stops flowing in the upper MOSFET and
is picked up by the low side MOSFET. Any
inductance in the switched path generates a large
voltage spike during the switching interval.
Careful component selections, layout of the
critical components, and use shorter and wider
PCB traces help in minimizing the magnitude of
voltage spikes.
2) The power components and the PWM controller
should be placed firstly. Place the input
capacitors, especially the high-frequency ceramic
decoupling capacitors, close to the power
switches. Place the output inductor and output
capacitors between the MOSFETs and the load.
Also locate the PWM controller near MOSFETs.
3) Use a dedicated grounding plane and use vias to
ground all critical components to this layer. Use
an immediate via to connect the component to
ground plane including GND of AP3586A/B/C.
4) Apply another solid layer as a power plane and
cut this plane into smaller islands of common
voltage levels. The power plane should support
the input power and output power nodes. Use
copper filled polygons on the top and bottom
circuit layers
for the PHASE node.
5) The PHASE node is subject to very high dV/dt
voltages. Stray capacitance between this island
and the surrounding circuitry tend to induce
current spike and capacitive noise coupling.
Keep the sensitive circuit away from the PHASE
node and keep the PCB area small to limit the
capacitive coupling. However, the PCB area
should be kept moderate since it also acts as
main heat convection path of the lower
MOSFET.
6) The PCB traces between the PWM controller and
the gate of MOSFET and also the traces
connecting source of MOSFETs should be sized
to carry 2A peak currents.
R2
R2 R1
0.6V V
OUT
+
× =
R2
R2 R1
0.8V V
OUT
+
Ч =