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Timing characteristics (continued) – Rainbow Electronics MAX1093 User Manual

Page 5

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MAX1091/MAX1093

250ksps, +3V, 8-/4-Channel, 10-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________

5

Note 1: Tested at V

DD

= +3V, COM = GND, unipolar single-ended input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have

been removed.

Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V

DD

.

Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.

TIMING CHARACTERISTICS (continued)

(V

DD

= V

LOGIC

= +2.7V to +3.6V, COM = GND, REFADJ = V

DD

, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 4.8MHz (50% duty

cycle), T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.)

t

TR

20

70

ns

C

LOAD

= 20pF, Figure 1

RD Rise to Output Disable
RD Fall to Output Data Valid

t

DO

20

70

ns

RD Fall to INT High Delay

t

INT1

100

ns

CS Fall to Output Data Valid

t

DO2

110

ns

C

LOAD

= 20pF, Figure 1

C

LOAD

= 20pF, Figure 1

C

LOAD

= 20pF, Figure 1

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

HBEN to Output Data Valid

t

DO1

20

110

ns

C

LOAD

= 20pF, Figure 1

3k

3k

DOUT

DOUT

V

LOGIC

a) HIGH-Z TO V

OH

AND V

OL

TO V

OH

b) HIGH-Z TO V

OL

AND V

OH

TO V

OL

C

LOAD

20pF

C

LOAD

20pF

Figure 1. Load Circuits for Enable/Disable Times