Rainbow Electronics MAX1093 User Manual

Page 13

MAX1091/MAX1093

250ksps, +3V, 8-/4-Channel, 10-Bit ADCs

with +2.5V Reference and Parallel Interface

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Selecting Clock Mode

The MAX1091/MAX1093 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The parts retain
the last requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock modes, internal or external acquisition
can be used. At power-up, the MAX1091/MAX1093
enter the default external clock mode.

Internal Clock Mode

Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. To select
this mode, bit D7 of the control byte must be set to 1
and D6 must be set to 0; the internal clock frequency is
then selected, resulting in a conversion time of 3.6µs.
When using the internal clock mode, tie the CLK pin
either high or low to prevent the pin from floating.

External Clock Mode

To select the external clock mode, bits D6 and D7 of
the control byte must be set to one. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1091/MAX1093 with
clock frequencies lower than 100kHz is not recom-
mended because it will cause a voltage droop across

the hold capacitor in the T/H stage that will result in
degraded performance.

Digital Interface

Input (control byte) and output data are multiplexed on
a three-state parallel interface. This parallel interface
(I/O) can easily be interfaced with standard µPs. The
signals CS, WR, and RD control the write and read
operations. CS represents the chip select signal, which
enables a µP to address the MAX1091/MAX1093 as an
I/O port. When high, CS disables the CLK WR and RD
inputs and forces the interface into a high-impedance
(high-Z) state.

Input Format

The control byte is latched into the device on pins
D7–D0 during a write command. Table 2 shows the
control byte format.

Output Format

The output format for both the MAX1091/MAX1093 is
binary in unipolar mode and two’s complement in bipo-
lar mode. When reading the output data, CS and RD
must be low. When HBEN = 0, the lower 8 bits are
read. With HBEN = 1, the upper 2 bits are available
and the output data bits D7–D2 are set either low in
unipolar mode or set to the value of the MSB in bipolar
mode (Table 5).

CLK

WR GOES HIGH WHEN CLK IS HIGH.

WR GOES HIGH WHEN CLK IS LOW.

CWS

CWH

ACQUISITION STARTS

CONVERSION STARTS

ACQUISITION ENDS

ACQMOD = "0"

Figure 6a. External Clock and

Timing (Internal Acquisition Mode)