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Electrical characteristics (continued) – Rainbow Electronics MAX1039 User Manual

Page 4

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MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

4

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ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= 2.7V to 3.6V (MAX1037/MAX1039), V

DD

= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V

REF

= 2.048V

(MAX1037/MAX1039), V

REF

= 4.096V (MAX1036/MAX1038). External clock, f

SCL

= 1.7MHz, T

A

= T

MIN

to T

MAX

, unless otherwise

noted. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIREMENTS

MAX1037/MAX1039

2.7

3.6

Supply Voltage (Note 10)

V

DD

MAX1036/MAX1038

4.5

5.5

V

Internal REF, external clock

350

650

f

SAMPLE

=

188ksps

External REF, external clock

250

External REF, external clock

110

f

SAMPLE

=

75ksps

External REF, internal clock

150

External REF, external clock

8

f

SAMPLE

=

10ksps

External REF, internal clock

10

External REF, external clock

2

f

SAMPLE

=

1ksps

External REF, internal clock

2.5

Supply Current

I

DD

Power-down

1

10

µA

Power-Supply Rejection Ratio

PSRR

(Note 11)

±0.25

±1

LSB/V

TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1A and 2)
Serial Clock Frequency

f

SCL

400

kHz

Bus Free Time Between a STOP
and a START Condition

t

BUF

1.3

µs

Hold Time for Start Condition

t

HD,

STA

0.6

µs

Low Period of the SCL Clock

t

LOW

1.3

µs

High Period of the SCL Clock

t

HIGH

0.6

µs

Setup Time for a Repeated START
Condition (Sr)

t

SU,

STA

0.6

µs

Data Hold Time

t

HD,

DAT

(Note 12)

0

150

ns

Data Setup Time

t

SU,

DAT

100

ns

Rise Time of Both SDA and SCL
Signals, Receiving

t

R

(Note 13)

20 + 0.1C

B

300

ns

Fall Time of SDA Transmitting

t

F

(Note 13)

20 + 0.1C

B

300

ns

Setup Time for STOP Condition

t

SU,

STO

0.6

µs

Capacitive Load for Each Bus Line

C

B

400

pF

Pulse Width of Spike Suppressed

t

SP

50

ns

TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1B and 2)

Serial Clock Frequency

f

SCLH

(Note 14)

1.7

MHz

Hold Time (Repeated) Start
Condition

t

HD,

STA

160

ns

Low Period of the SCL Clock

t

LOW

320

ns

High Period of the SCL Clock

t

HIGH

120

ns