Rainbow Electronics MAX3673 User Manual

Page 10

MAX3673

Low-Jitter Frequency Synthesizer
with Selectable Input Reference

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IN0FAIL and IN1FAIL, respectively. Once an indicator
is asserted low, it is latched and updated every 128
PFD cycles (~ 2µs).

It should be noted that when the PLL is locked to a ref-
erence clock, the clock failure indicator for the other
reference clock is only valid for amplitude qualification
and frequency qualification.

Amplitude Qualification

A reference clock input fails amplitude qualification if
any of the following conditions occur:

• Either one or both inputs (REFCLKx, REFCLKx) are

shorted to V

or GND.

• Both inputs (REFCLKx, REFCLKx) are disconnect-

ed from the source and have 130

Ω to V

and 82

to GND at each input. See Figure 3.

• Input reference clock differential swing is below the

clock failure assert threshold as specified in the

Electrical Characteristics

. See Figure 4.

The response time for these conditions is typically
between 50ns and 300ns.

Phase Qualification

A reference clock input fails phase qualification when
the phase error at the PFD output exceeds the error
window (0.75ns typical) for more than five of eight PFD
cycles. A reference clock input is qualified when phase
error at the PFD output is within the phase-error window
for eight consecutive PFD cycles. Note that phase qual-
ification only applies to the reference input currently
being used by the PLL.

Frequency Qualification

A reference clock input becomes frequency qualified if
the input frequency is within ±2.4% of the nominal fre-
quency. The reference input becomes frequency dis-
qualified if the input frequency moves away from the
nominal frequency by more than ±8%.

130

LVPECL

130

BOTH INPUTS

OPEN

MAX3673

DIFFERENTIAL INPUT: (REFCLKx - REFCLKx)

Figure 3. Positions for Open-Circuit Detection

Figure 4. Input Amplitude Detection Threshold