Rainbow Electronics MAX1121 - Manual (Page 10)

MAX1121
Detailed Description—
Theory of Operation
The MAX1121 uses a fully differential, pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy and linearity, while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a common-
mode voltage of 1.4V, and accept a differential analog
input voltage swing of ±0.3125V each, resulting in a typi-
cal differential full-scale signal swing of 1.25V
P-P .
INP and INN are buffered prior to entering each track-
and-hold (T/H) stage and are sampled when the differen-
tial sampling clock signal transitions high. A 2-bit ADC
following the first T/H stage then digitizes the signal, and
controls a 2-bit digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 8-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital cor-
rection logic to generate the final output code. The result
is a 8-bit parallel digital output word in user-selectable
two’s complement or binary output formats with LVDS-
compatible output levels. See Figure 1 for a more
detailed view of the MAX1121 architecture.
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1121. Differential inputs usually feature good rejec-
tion of even-order harmonics, which allows for enhanced
AC performance as the signals are progressing through
the analog stages. The MAX1121 analog inputs are self-
biased at a common-mode voltage of 1.4V and allow a
differential input voltage swing of 1.25V
P-P . Both inputs
are self-biased through 2.2kΩ resistors, resulting in a
typical differential input resistance of 4.4kΩ. It is recom-
mended to drive the analog inputs of the MAX1121 in
AC-coupled configuration to achieve best dynamic per-
formance. See the AC-Coupled Analog Inputs section for
a detailed discussion of this configuration.
On-Chip Reference Circuit
The MAX1121 features an internal 1.23V bandgap ref-
erence circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the full-
scale range of the MAX1121. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain
errors or increase the ADC’s full-scale range, the volt-
age of this bandgap reference can be indirectly adjust-
ed by adding an external resistor (e.g., 100kΩ trim
potentiometer) between REFADJ and AGND or
REFADJ and REFIO. See the Applications Information
section for a detailed description of this process.
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1121
with an LVDS-compatible clock to achieve the best
dynamic performance. The clock signal source must be
a high-quality, low phase noise to avoid any degrada-
tion in the noise performance of the ADC. The clock
inputs (CLKP, CLKN) are internally biased to 1.2V,
accept a differential signal swing of 0.2V
P-P to 1.0V P-P
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
10 ______________________________________________________________________________________
AV
CC
AGND
INN INP
TO COMMON-MODE INPUT
2.2kΩ
TO COMMON-MODE INPUT
2.2kΩ
Figure 2. Simplified Analog Input Architecture
REFERENCE
BUFFER REFIO
REFADJ
AV CC AV CC / 2
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
ADC FULL-SCALE = REFT - REFB
G
1V
1kΩ
0.1µF
REFERENCE
SCALING
AMPLIFIER REFT
REFB
Figure 3. Simplified Reference Architecture