Rainbow Electronics MAX1068 - Manual (Page 5)

MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
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ELECTRICAL CHARACTERISTICS (continued)
(AV DD = DV DD = +4.75V to +5.25V, f SCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external V REF
= +4.096V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Shutdown Supply Current
I AVDD +
I DVDD
CS = DV
DD , SCLK = 0, DIN = 0,
DSPR = DV DD , full power-down
0.6 10 µA
Power-Supply Rejection Ratio PSRR
AV DD = DV DD = 4.75V to 5.25V, full-scale
input (Note 9)
63 dB
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(AV DD = DV DD = +4.75V to +5.25V, f SCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external V REF
= +4.096V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time t ACQ External clock (Note 6) 729 ns
SCLK to DOUT Valid t DO C DOUT = 30pF 50 ns
CS Fall to DOUT Enable t DV C DOUT = 30pF 80 ns
CS Rise to DOUT Disable t TR C DOUT = 30pF 80 ns
CS Pulse Width t CSW 100 ns
SCLK rise
CS to SCLK Setup t CSS
SCLK fall (DSP)
100 ns
SCLK rise
CS to SCLK Hold t CSH
SCLK fall (DSP)
0 ns
Conversion 93
SCLK High Pulse Width t CH Duty cycle 45% to 55%
Data transfer 50
ns
Conversion 93
SCLK Low Pulse Width t CL Duty cycle 45% to 55%
Data transfer 50
ns
SCLK Period t CP 209 ns
SCLK rise
DIN to SCLK Setup t DS
SCLK fall (DSP)
50 ns
SCLK rise
DIN to SCLK Hold t DH
SCLK fall (DSP)
0 ns
CS Falling to DSPR Rising t DF 100 ns
DSPR to SCLK Falling Setup t FSS 100 ns
DSPR to SCLK Falling Hold t FSH 0 ns