Ds1372, C, 32-bit, binary counter clock with 64-bit id – Rainbow Electronics DS1372 User Manual
Page 9
conditions. The DS1372 operates as a slave on the I
2
C
bus. Connections to the bus are made through the SCL
input and open-drain SDA I/O lines. Within the bus
specifications, a standard mode (100kHz maximum
clock rate) and a fast mode (400kHz maximum clock
rate) are defined. The DS1372 works in both modes.
The following bus protocol has been defined (Figure 5):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
DS1372
_______________________________________________________________________________________
9
SDA
SCL
t
HD:STA
t
LOW
t
HIGH
t
R
t
F
t
BUF
t
HD:DAT
t
SU:DAT
REPEATED
START
t
SU:STA
t
HD:STA
t
SU:STO
t
SP
STOP
START
Figure 4. Data Transfer on I
2
C Serial Bus
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
1
2
6
7
8
9
1
2
8
9
3–7
Figure 5. I
2
C Data Transfer Overview
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID