Rainbow Electronics ADC08L060 - Manual (Page 16)

Applications Information
(Continued)
4.2.2 Clock Line Termination
The CLOCK line should be series terminated at the clock
source in the characteristic impedance of that line. If the
clock line is longer than
where t
r
is the clock rise time and t
prop
is the propagation rate
of the signal along the trace. The CLOCK pin should be a.c.
terminated with a series RC to ground such that the resistor
value is equal to the characteristic impedance of the clock
line and the capacitor value is
where “L” is the line length in inches and Z
O
is the charac-
teristic impedance of the clock line. Typical t
PROP
is about
150 ps/inch on FR-4 board material. For FR-4 board mate-
rial, the value of C becomes
This termination should be located as close as possible to,
but within one centimeter of, the ADC08L060 clock pin.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are es-
sential to ensure accurate conversion. A combined analog
and digital ground plane should be used.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise
because of the skin effect. Total surface area is more impor-
tant than is total ground plane volume. Capacitive coupling
between the typically noisy digital circuitry and the sensitive
analog circuitry can lead to poor performance that may seem
impossible to isolate and remedy. The solution is to keep the
analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or
near a straight line between the ADC or any linear compo-
nent and the power supply area as the resulting common
return current path could cause fluctuation in the analog
input “ground” return of the ADC.
Keeping analog and digital return (ground) currents separate
from each other will improve system noise performance. Two
methods may be used to do this. Use of traces rather than a
solid plane to route power to all components will accomplish
this because return currents follow the path of the outgoing
currents. However, the advantage of the distributed capaci-
tance of a power plane and a ground plane is lost. Analog
and digital power should be routed as far from each other as
is practical. The analog power trace should also be routed
away from digital areas of the board.
The use of power and ground planes in adjacent layers will
provide distributed capacitance for a low impedance power
distribution system and better system noise performance.
The use of separate analog and digital power planes, both in
the same PC board layer, and the use of a single, non-split
ground plane will keep analog and digital currents separated
from each other. Of course, locate all analog circuitry and
traces over the analog power plane and the digital circuitry
and traces over the digital power plane. To minimize RFI/
EMI, give proper attention to any lines crossing the analog/
digital power plane boundary.
Noise performance is also enhanced by driving a single gate
with each ADC output pin and locating the gate as close as
possible to the ADC output. Inserting a 47
Ω resistor in series
with the ADC digital output pins will also help reduce ADC
noise. Be sure to keep the resistors as close to the ADC
output pins as possible. Eliminating ground plane copper
beneath the ADC output lines can also help ADC noise
performance, but could produce unacceptable radiation from
the board.
Analog and digital circuitry should be kept well away from
each other. Especially troublesome is high power digital
components such as processors and large PLDs. Switch
mode power supplies, including capacitive DC-DC convert-
ers, can cause noise problems with high speed ADCs. Keep
such components well away from ADCs and low level analog
signal areas. Such components should be located as close
to the power supply as possible and should not be in the path
of analog signal or power supply currents.
Digital circuits create substantial supply and ground current
transients. The noise thus generated could have significant
impact upon system noise performance. The best logic fam-
ily to use in systems with A/D converters is one that employs
non-saturating transistor designs, or has low noise charac-
teristics, like the 74LS and the 74AC(T)Q families. The worst
noise generators are logic families that draw the largest
supply current transients during clock or signal edges, like
the 74HC, 74F and 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon logic-generated noise. This
is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Clock lines should be isolated from ALL other lines, analog
AND digital. Even the generally accepted 90˚ crossing
should be avoided as even a little coupling can cause prob-
lems at high frequencies. Best performance at high frequen-
cies is obtained with a straight signal path.
20041736
FIGURE 5. Layout Example
ADC08L060
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