Rainbow Electronics DS2411 - Manual (Page 10)

DS2411
10 of 11
Slave to Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below
V
TLMIN
until the read low time t
RL
is expired. During the t
RL
window, when responding with a 0, the
DS2411 will start pulling the data line low; its internal timing generator determines when this pull-down
ends and the voltage starts rising again. When responding with a 1, the DS2411 will not hold the data line
low at all, and the voltage starts rising as soon as t
RL
is over.
The sum of t
RL
+ d (rise rime) on one side and the internal timing generator of the DS2411 on the other
side define the master sampling window (t
MSRMIN
to t
MSRMAX
) in which the master must perform a read
from the data line. For most reliable communication, t
RL
should be as short as permissible and the master
should read close to but no later than t
MSRMAX
. After reading from the data line, the master must wait until
t
SLOT
is expired. This guarantees sufficient recovery time t
REC
for the DS2411 to get ready for the next
time slot.
Improved Network Behavior
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks therefore are susceptible to noise of various origins. Depending on the
physical size and topology of the network, reflections from end points and branch points can add up or
cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire
communication line. A glitch during the rising edge of a time slot can cause a slave device to lose
synchronization with the master and, as a consequence, result in a search ROM command coming to a
dead end. For better performance in network applications, the DS2411 uses a new 1-Wire front end,
which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave
device itself.
The 1-Wire front end of the DS2411 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the
line impedance than a digitally switched transistor, converting the high frequency ringing known from
traditional devices into a smoother low-bandwidth transition. The slew rate control is specified by the
parameter t
FPD
, which has different values for standard and Overdrive speed.
2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a
time slot. This reduces the sensitivity to high-frequency noise. As a consequence, the duration of the
setup time t
SU
at standard speed is larger than with traditional devices. This additional filtering does
not apply at Overdrive speed.
3) There is a hysteresis at the low-to-high switching threshold V
TH
. If a negative glitch crosses V
TH
but
doesn’t go below V
TH
- V
HY
, it will not be recognized (Figure 8, Case A). The hysteresis is effective
at any 1-Wire speed.
4) There is a time window specified by the rising edge hold-off time t
REH
during which glitches will be
ignored, even if they extend below V
TH
- V
HY
threshold (Figure 8, Case B, t
GL
< t
REH
). Deep voltage
droops or glitches that appear late after crossing the V
TH
threshold and extend beyond the t
REH
window cannot be filtered out and will be taken as beginning of a new time slot (Figure 8, Case C, t
GL
³ t
REH
). The duration of the hold-off time is independent of the 1-Wire speed.
Only devices which have the parameters t
FPD
, V
HY
and t
REH
specified in their electrical characteristics use
the improved 1-Wire front end.