Rainbow Electronics DS1302 - Manual (Page 12)

DS1302
12 of 15
TIMING DIAGRAM: READ DATA TRANSFER Figure 5
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
NOTES:
1. I
CC1T
and I
CC2T
are specified with I/O open, RST set to a logic 0, and clock halt flag = 0 (oscillator
enabled).
2. I
CC1A
and I
CC2A
are specified with the I/O pin open, RST high, SCLK=2MHz at V
CC
= 5V;
SCLK = 500kHz, V
CC
= 2.0V, and clock halt flag = 0 (oscillator enabled).
3. RST , SCLK, and I/O all have 40kΩ pull-down resistors to ground.
4. Measured at V
IH
= 2.0V or V
IL
= 0.8V and 10ns maximum rise and fall time.
5. Measured at V
OH
= 2.4V or V
OL
= 0.4V.
6. Load capacitance = 50pF.
7. I
CC1S
and I
CC2S
are specified with RST , I/O, and SCLK open. The clock halt flag must be set to logic
one (oscillator disabled).
8. V
CC
= V
CC2
, when V
CC2
> V
CC1
+ 0.2V; V
CC
= V
CC1
, when V
CC1
> V
CC2
.
9. V
CC2
= 0V.
10. V
CC1
= 0V.
11. Typical values are at 25°C.