Rainbow Electronics DS2784 - Manual (Page 37)

DS2784: 1-Cell Stand-Alone Fuel Gauge IC with Li+ Protector and SHA-1 Authentication
I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the DS2784
are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data.
The bus master initiates all these types of signaling except the presence pulse.
The initialization sequence required to begin any communication with the DS2784 is shown in Figure 13. A
presence pulse following a reset pulse indicates that the DS2784 is ready to accept a net address command. The
bus master transmits (Tx) a reset pulse for t
RSTL
. The bus master then releases the line and goes into Receive
mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ
pin, the DS2784 waits for t
PDH
and then transmits the presence pulse for t
PDL
.
Figure 13. 1-Wire Initialization Sequence
t
RSTL
t
PDL
t
RSTH
t
PDH
PACK+
PACK-
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW DS2784 ACTIVE LOW
RESISTOR PULLUP BOTH BUS MASTER AND
DS2784 ACTIVE LOW
DQ
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and write 0. All write-time slots must be t
SLOT
in duration with a
1 μs minimum recovery time, t
REC
, between cycles. The DS2784 samples the 1-Wire bus line between t
LOW1_MAX
and
t
LOW0_MIN
after the line falls. If the line is high when sampled, a write 1 occurs. If the line is low when sampled, a
write 0 occurs. The sample window is illustrated in Figure 14. For the bus master to generate a write-1 time slot, the
bus line must be pulled low and then released, allowing the line to be pulled high less than t
RDV
after the start of the
write time slot. For the host to generate a write 0 time slot, the bus line must be pulled low and held low for the
duration of the write-time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.
The bus master must keep the bus line low for at least 1
μs and then release it to allow the DS2784 to present valid
data. The bus master can then sample the data t
RDV
from the start of the read-time slot. By the end of the read-time
slot, the DS2784 releases the bus line and allows it to be pulled high by the external pullup resistor. All read-time
slots must be t
SLOT
in duration with a 1 μs minimum recovery time, t
REC
, between cycles. See Figure 14 and the
timing specifications in the Electrical Characteristics table for more information.
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