Rainbow Electronics ADC10D040 - Manual (Page 25)

Applications Information
(Continued)
2.2 V
CMO
Output
The V
CMO
output pin is intended to provide a common mode
bias for the differential input pins of the ADC10D040. It can
also be used as a voltage reference source. Care should be
taken, however, to avoid loading this pin with more than 1
mA. A load greater than this could result in degraded long
term and temperature stability of this voltage. The V
CMO
pin
is output compensated and should be bypassed with a
1 µF/0.1 µF combination, minimum. See 2.0 REFERENCE
INPUTS for more information on using the V
CMO
output as a
reference source.
3.0 DIGITAL INPUT PINS
The seven digital input pins are used to control the function
of the ADC10D040.
3.1 The Adc Clock (CLK) Input
The clock (CLK) input is common to both A/D converters.
This pin is CMOS/LVTTL compatible with a threshold of
about V
A
/2. Although the ADC10D040 is tested and its per-
formance is guaranteed with a 40 MHz clock, it typically will
function well with low-jitter clock frequencies from 20 MHz to
45 MHz. The analog inputs I = (I+) – (I−) and Q = (Q+) –
(Q−) are simultaneously sampled on the falling edge of this
input to ensure the best possible aperture delay match be-
tween the two channels.
3.1.1 Low Sample Rate Considerations
While the ADC10D040 will typically function well with sample
rates below 20 MSPS, it is important to note that it is possible
for some production lots not to perform well below 20 MSPS.
To ensure adequate performance over lot to lot and over
temperature extremes, we recommend not operating the
ADC10D040 at sample rates below 20 MSPS.
3.1.2 Clock Termination
The clock source should be series terminated to match the
clock source impedance with the characteristic impedance of
the clock line, Z
O
. It may also be necessary to a.c. terminate
the ADC clock pin with a series RC to ground. This series
network should be located near the ADC10D040 clock pin
but on the far side of that pin as seen from the clock source.
The resistor value should equal the characteristic imped-
ance, Z
O
, of the clock line and the capacitor should have a
value such that C x Z
O
≥ 4 x t
PD
, where t
PD
is the time of
propagation of the clock signal from its source to the ADC
clock pin. The typical propagation rate on a board of FR4
material is about 150 ps/inch. The rise and fall times of the
clock supplied to the ADC clock pin should be no more than
4 ns.
3.2 Output Bus Select (OS) Pin
The Output Bus Select (OS) pin determines whether the
ADC10D040 is in the parallel or multiplexed mode of opera-
tion. A logic high at this pin puts the device into the parallel
mode of operation where “I” and “Q” data appear at their
respective output buses. A logic low at this pin puts the
device into the multiplexed mode of operation where the “I”
and “Q” data are multiplexed onto the “I” output bus and the
“Q” output lines all remain at a logic low.
3.3 Offset Correct (OC) Pin
The Offset Correct (OC) pin is used to initiate an offset
correction sequence. This procedure should be done after
power up and need not be performed again unless power to
the ADC10D040 is interrupted. An independent offset cor-
rection sequence for each converter is initiated when there is
a low-to-high transition at the OC pin. This sequence takes
34 clock cycles to complete, during which time 32 conver-
sions are taken and averaged. The result is subtracted from
subsequent conversions. Because the offset correction is
performed digitally at the output of the ADC, the output range
of the ADC is reduced by the offset amount.
Each input pair should have a 0V differential voltage value
during this entire 34 clock period, but the “I” and “Q” input
common mode voltages do not have to be equal to each
other. Because of the uncertainty as to exactly when the
correction sequence starts, it is best to allow 35 clock peri-
ods for this sequence.
3.4 Output Format (OF) Pin
The Output Format (OF) pin provides a choice of straight
binary or 2’s complement output formatting. With this pin at a
logic low, the output format is straight binary. With this pin at
a logic high, the output format is 2’s complement.
3.5 Standby (STBY) Pin
The Standby (STBY) pin may be used to put the
ADC10D040 into a low power mode where it consumes just
30 mW and can quickly be brought to full operation. The
device operates normally with a logic low on this and the PD
pins.
While in the Standby mode the data outputs contain the
results of the last conversion before going into this Mode.
3.6 Power Down (PD) Pin
The Power Down (PD) pin puts the device into a low-power
“sleep” state where it consumes less than 1 mW when the
PD pin is at a logic high. Power consumption is reduced
more when the PD pin is high than when the STBY pin is
high, but recovery to full operation is much quicker from the
standby state than it is from the power down state. When the
STBY and PD pins are both high, the ADC10D040 is in the
power down mode.
While in the Power Down mode the data outputs contain the
results of the last conversion before going into this mode.
3.7 GAIN Pin
The GAIN pin sets the internal signal gain of the “I” and “Q”
inputs. With this pin at a logic low, the full scale differential
peak-to-peak input signal is equal to V
REF
. With the GAIN
pin at a logic high, the full scale differential peak-to-peak
input signal is equal to 2 times V
REF
.
4.0 INPUT/OUTPUT RELATIONSHIP ALTERNATIVES
The GAIN pin of the ADC10D040 offers input range selec-
tion, while the OF pin offers a choice of straight binary or 2’s
complement output formatting.
The relationship between the GAIN, OF, analog inputs and
the output code are as defined in Table 1. Keep in mind that
the input signals must not exceed the power supply rails.
ADC10D040
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