Rainbow Electronics MAX5098A User Manual
Page 19
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MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
______________________________________________________________________________________
19
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX5098A: inductance value (L),
peak inductor current (I
L
), and inductor saturation cur-
rent (I
SAT
). The minimum required inductance is a func-
tion of operating frequency, input-to-output voltage
differential and the peak-to-peak inductor current (ΔI
L
).
A good compromise is to choose ΔI
L
equal to 30% of
the full load current. To calculate the inductance, use
the following equation:
where V
IN
and V
OUT
are typical values (so that efficien-
cy is optimum for typical conditions). The switching fre-
quency is set by R
OSC
(see the
Setting the Switching
Frequency
section). The peak-to-peak inductor current,
which reflects the peak-to-peak output ripple, is worse
at the maximum input voltage. See the
Output
Capacitor
section to verify that the worst-case output
ripple is acceptable. The inductor saturation current is
also important to avoid runaway current during output
overload and continuous short circuit. Select the I
SAT
to
be higher than the maximum peak current limits of 4.3A
and 2.6A for converter 1 and converter 2.
Input Capacitor
The discontinuous input current waveform of the buck
converter causes large ripple currents at the input. The
switching frequency, peak inductor current, and the
allowable peak-to-peak voltage ripple dictate the input
capacitance requirement. Note that the two converters
of the MAX5098A run 180° out-of-phase, thereby effec-
tively doubling the switching frequency at the input.
The input ripple waveform would be unsymmetrical due
to the difference in load current and duty cycle
between converter 1 and converter 2. The worst-case
mismatch is when one converter is at full load while the
other converter is at no load or in shutdown. The input
ripple is comprised of ΔV
Q
(caused by the capacitor
discharge) and ΔV
ESR
(caused by the ESR of the
capacitor). Use ceramic capacitors with high ripple-
current capability at the input, connected between
DRAIN_ and PGND_. Assume the contribution from the
ESR and capacitor discharge equal to 50%. Calculate
the input capacitance and ESR required for a specified
ripple using the following equations:
where
and
where
where I
OUT
is the maximum output current from either
converter 1 or converter 2, and D is the duty cycle for
that converter. The frequency of each individual con-
verter is f
SW
. For example, at V
IN
= 12V, V
OUT
= 3.3V at
I
OUT
= 2A, and with L = 3.3µH, the ESR and input
capacitance are calculated for a peak-to-peak input rip-
ple of 100mV or less, yielding an ESR and capacitance
value of 20mΩ and 6.8µF for 1.25MHz frequency. At low
input voltages, also add one electrolytic bulk capacitor
of at least 100µF on the converters’ input voltage rail.
This capacitor acts as an energy reservoir to avoid pos-
sible undershoot below the undervoltage lockout thresh-
old during power-on and transient loading.
Output Capacitor
The allowable output ripple voltage and the maximum
deviation of the output voltage during step load cur-
rents determines the output capacitance and its ESR.
The output ripple is comprised of ΔV
Q
(caused by the
capacitor discharge) and ΔV
ESR
(caused by the ESR of
the capacitor). Use low-ESR ceramic or aluminum elec-
trolytic capacitors at the output. For aluminum elec-
trolytic capacitors, the entire output ripple is
contributed by ΔV
ESR
. Use the ESR
OUT
equation to cal-
culate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume the
contribution to the output ripple voltage from the ESR
and the capacitor discharge are equal. Calculate the
output capacitance and ESR required for a specified
ripple using the following equations:
ESR
V
I
C
I
V
f
OUT
ESR
L
OUT
L
Q
SW
=
=
Ч
Ч
Δ
Δ
Δ
Δ
8
D
V
V
OUT
IN
=
C
I
D
D
V
f
IN
OUT
Q
SW
=
Ч
( )
Ч
−
1
Δ
ΔI
V
V
V
V
f
L
L
IN
OUT
OUT
IN
SW
=
(
)
Ч
Ч
Ч
−
ESR
V
I
I
IN
ESR
OUT
L
=
+
Δ
Δ
2
L
V
V
V
V
f
I
OUT
IN
OUT
IN
SW
L
=
(
)
Ч
Ч
−
Δ