Functional block diagram – Texas Instruments TPA3008D2 User Manual

Page 4

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Biases

and

References

TTL Input

Buffer

(VCC Compl)

Start-up and

Protection

Logic

SC

Detect

Thermal

VDDok

RINP

RINN

Ramp
Generator

COSC

ROSC

VCCok

5-V LDO

AVCC

AVDD

AVDD

VDD

and

PWM
Mode

Logic

Gain

Adj.

Gain

Control

Deglitch

and

PWM
Mode

Logic

Gain

Adj.

LINP

LINN

Gate

Drive

VClamp

Gen

Gate

Drive

PVCC

BSRP
PVCCR(2)

ROUTP(2)

PGNDR

PGNDR

ROUTN(2)

PVCCR(2)

BSRN

Gate

Drive

VClamp

Gen

Gate

Drive

PVCC

BSLP
PVCCL(2)

LOUTP(2)

PGNDL

PGNDL

LOUTN(2)

PVCCL(2)

BSLN

VCLAMPL

VCLAMPR

GAIN0

4

To Gain Adj.

Blocks and
Start-up Logic

SHUTDOWN

V2P5

V2P5

V2P5

AVCC

AGND(2)

V2P5

V2P5

Deglitch

GAIN1

AV

DD

REF

FAULT

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

FUNCTIONAL BLOCK DIAGRAM

4