Renesas HD151TS207SS - Manual (Page 36)

HD151TS207SS
Rev.1.00, Apr.25.2003, page 36 of 38
Clock Out
tcycle n
t = (tcycle n) - (tcycle n+1)
CCS
tcycle n+1
Fig.1 Cycle to Cycle Jitter (3.3V Single Ended Clock Output)
Clock Outx
Clock Outy
1.5 V
tskS
1.5 V
Fig.2 Output Clock Skew (3.3V Single Ended Clock Output)
R
P
=
49.9 Ω
R
P
=
49.9 Ω
Z
LT
= Z
LC
= 50
Ω
R
S
= 33.2
Ω
CPU LT
CPU#
TS207
C
L
= 2 pF C
L
= 2 pF
R
S
= 33.2 Ω
LC
R
I(ref)
=
475 Ω
Fig.3 Load Circuit for CPU/CPU#