Renesas HD151TS207SS - Manual (Page 12)

HD151TS207SS
Rev.1.00, Apr.25.2003, page 12 of 38
I
2
C Controlled Register Bit Map (cont.)
Byte9 Control Register
Bit Description Contents Type Default Note
7 SSC2 Enable Bit B6[2] = 0 or B9[7] = 1 : SSC2 =OFF
B6[2] = 1 & B9[7] = 0 : SSC2 = ON RW 0
6 SSC1 Enable Bit B6[2] = 0 or B9[6] = 1 : SSC1 = OFF
B6[2] = 1 & B9[6] = 0 : SSC1 = ON RW 0
5 Clock Frequency Control
Bit4 Latched input PCIF_1 at Power ON RW X
4 Clock Frequency Control
Bit3 Latched input DOT48 at Power ON RW X
3 Clock Frequency Control
Bit2 Latched input PCIF_0 at Power ON RW X
2 Clock Frequency Control
Bit1 Latched input FS_A at Power ON RW X
1 Clock Frequency Control
Bit0 Latched input FS_B at Power ON RW X
See
Table
6
0 Frequency Select Mode Bit 0 = Freq. is selected by latched input
FS_A and FS_B
1 = Freq. is selected by I
2
C B9[5:1]
RW 0