Renesas SuperH SH7339 - Manual (Page 20)

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13. Memory Access during Break
In the enabled MMU, when a memory is accessed and a TLB error occurs during break, it can
be selected whether the TLB exception is controlled or the program jumps to the user
exception handler in [TLB Mode] in the [Configuration] dialog box. When [TLB miss
exception is enable] is selected, a “Communication Timeout error” will occur if the TLB
exception handler does not operate correctly. When [TLB miss exception is disable] is
selected, the program does not jump to the TLB exception handler even if a TLB exception
occurs. Therefore, if the TLB exception handler does not operate correctly, a “Communication
Timeout error” will not occur but the memory contents may not be correctly displayed.
14. Loading Sessions
Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading
sessions. Thus the TCK value will be as follows:
•
When HS0005KCU01H or HS0005KCU02H is used: TCK = 0.625 MHz
15. [IO] window
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Display and modification
Do not change values of the User Break Controller because it is used by the emulator.
For each watchdog timer and RCLK watchdog timer register, there are two registers to be
separately used for write and read operations.
Table 2.3 Watchdog Timer Register
Register Name Usage Register
WTCSR(W) Write Watchdog timer control/status register
WTCNT(W) Write Watchdog timer counter
WTCSR(R) Read Watchdog timer control/status register
WTCNT(R) Read Watchdog timer counter
RWTCSR(W) Write RCLK watchdog timer control/status register
RWTCNT(W) Write RCLK watchdog timer counter
RWTCSR(R) Read RCLK watchdog timer control/status register
RWTCNT(R) Read RCLK watchdog timer counter
•
The watchdog timer operates only when the user program is executed. Do not change the
value of the frequency change register in the [IO] window or [Memory] window.