Nvidia NFORCE 780I SLI - Manual (Page 85)

Using NVIDIA Software
NVIDIA Corporation
October 17, 2007 | DU-03597-001_v01 75
q Write Recovery Time
Memory timing that determines the delay between a write command and a
Precharge command is set to the same bank of memory. Adjustable from 1 to
15.
q W to R Termination Turnaround
The Write-to-Read time is the number of clock cycles between the last write
data pair and the subsequent READ command to the same physical block.
Adjustable from 1 to 15.
q RAS to CAS access
The RAS-to-CAS access (tRCD) is the amount of time in cycles for issuing an
active command and the read/write commands. Adjustable from 1 to 15.
q RAS to RAS Delay
The RAS-to-RAS delay (tRRD) is the is the amount of cycles it takes to
activate the next bank of memory (this is the opposite of tRAS). The lower
the timing the better the system performance. However, this scenario can
cause instability. Adjustable from 1 to 15.
q Refresh Rate
This value is filled in by the system and can not be changed by the user.
q Memory bank switch
The row Precharge time (tRP) is the minimum time between active
commands and the read/writes of the next bank on the memory module.
Adjustable from 1 to 15.
q R to W Turnaround
The Read-to-Write turnaround (tRWT) is a the amount of cycles for the
command to be executed when a Write command is received. Adjustable
from 1 to 15.
q R to R Timing
the Read-to-Read time (tRDRD) is the number of clock cycles between the
last read and the subsequent READ command to the same physical bank.
Adjustable from 1 to 15.
q Row Cycle Time
The Row Cycle Time is the minimum time in cycles it take a row to complete
a full cycle. This can be determined by tRC=tRAS+tRP. If this value is set
too short, it can cause corruption of data. If this value is set too high, it causes
a loss in performance but an increase in stability. Adjustable from 1 to 63
cycles