Paradyne ACCULINK 3161 CSU - Manual (Page 8)

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Table 2. Port Configuration Options (2 of 3)
Option Comments/Description Factory 2 Factory 1
Disab Disab
Port LB:
DTLB DTLB Port-initiated Loopbacks, allows
Loopbacks to be initiated through
Port LB:
DCLB DCLB
p ,
Loopbacks to be initiated through
the port by the external DTE.
Both Both
e po by e e e a
Disab Disab
All Ones:
DTR DTR
All ones sent to network (DTE) T1
All Ones:
RTS RTS
All ones sent to network (DTE) T1
when DTR or RTS interrupted.
Both Both
Rcv Yellow:
None None Data port remains enabled, or is
disabled on receiving Yellow on
Rcv Yellow:
(Received Yellow)
Halt Halt
p ,
disabled, on receiving Yellow on
network T1.
Tx Clock:
Int Int Selects whether the transmitted
data clock is internal (TXC) or
Tx Clock:
Ext Ext
data clock is internal (TXC) or
external (XTXC).
InvertTxC:
Enab Enab
Selects phase inversion of the InvertTxC:
(Invert Tx Clock)
Disab Disab
Selects phase inversion of the
transmit clock (TXC).
InvertData:
Enab Enab
Allows the data on the port to be
InvertData:
Disab Disab
Allows the data on the port to be
inverted.
EDL:
Enab Enab
Specifies whether the Embedded
EDL:
Disab Disab
Specifies whether the Embedded
Data Link is enabled.
10E–4 10E–4
10E–5 10E–5
Err Rate:
(Excessive Error 10E–6 10E–6 Selects the error rate threshold for
Excessive Error Rate Alarm
(Excessive Error
Rate)
10E–7 10E–7
Excessive Error Rate Alarm.
a e)
10E–8 10E–8
10E–9 10E–9
Disab Disab
Near end:
Maint Maint Specifies whether the device will
maintain near end performance
Near-end:
Send Send
p
maintain near-end performance
statistics.
Both Both
s a s cs