LSI 21003 - Manual (Page 14)

1-4 Using the LSI21003
functionality for the LSI21003 is contained within the LSI53C1010-33.
The chip connects directly to the PCI bus and generates timing protocol
in compliance with the PCI specification.
The PCI interface operates as a 32-bit DMA bus master. The connection
is made through edge connector J1 (see
Figure 2.1 ). The signal
definitions and pin numbers conform to the PCI Local Bus Specification
Revision 2.2 standard. The LSI21003 conforms to the PCI universal
signaling environment for a 5 V or 3.3 V PCI bus.
1.3.2 The SCSI Interface
The SCSI functionality for the host adapter is also contained within the
LSI53C1010-33. The chip connects directly to the two SCSI buses for SE
or LVD SCSI applications and generates timing and protocol in
compliance with SCSI standards. One SCSI interface operates at a burst
transfer rate of up to 40 Mbytes/s for wide Ultra SCSI transfers, and the
other up to 160 Mbytes/s for wide Ultra160 SCSI transfers.
Channel A is SE only with active autosensing termination. The
Channel A interface is made through connectors J2, J3, and J4.
Connector J2 is a 68-pin high density right-angle receptacle for internal
SCSI connections. Connector J3 is a 50-pin high density right-angle
receptacle that protrudes through the ISA/EISA bracket. Connector J4 is
a 50-pin narrow (ribbon) internal connector.
Channel B may be either SE or LVD with active termination always
enabled. The Channel B interface is made through connector J5. J5 is a
68-pin high density right-angle connector for internal SCSI connections.
See Figure 2.1 on page 2-5 for the location of these connectors.
The LSI21003 supplies SCSI bus TERMPWR through a blocking diode
and self-resetting 1.5 A short circuit protection device.
A 40 MHz oscillator on the host adapter provides the clock frequency to
the LSI53C1010-33 that is necessary to support SCSI transfers.