Sharp ER-A440 - Manual (Page 10)

2) Block diagram
Fig. 2-2
P47
FTI2
P45
FTI1
P43
P42
P41/TMCI
P40
P37
P36
P35
P34
P33
BREQ
BACK
WAIT
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AVCC
AVSS
MD2
MD1
MD0
RES
STBY
NMI
AS
RD
HWR
LWR
RFSH
EXTAL
XTAL
E
P17 P16 P15 P14 P13 P12 P11 P10 D7 D6 D5 D4 D3 D2 D1 D0
STOP/P57
P56
FM
RS
P54 P53 P52 P51 P50 P67 P66
RS/P65 RR/P64 CD/P63 CS/P62 DR/P61 ER/P60
P73 AN2 AN1 AN0
TX
D2
RXD2 TX
D1
RXD1 SCK2
IR
Q2
IR
Q1
IR
Q0
H8/500 CPU DTC
Serial
communication
interface x 2ch
8bit timer
16bit free running
timer x 2ch
Refresh controller
Wait state
controller
A/D convertor
Interruption controller
Clock
oscillator Watch
dog timer
Data bus Port 1
Data bus (Lower) Data bus (Upper) Address bus
Port 2
Port 3
Port 4
Port 5 Port 6 Port 7 Port 8
Address bus
X
4 – 3