SUPER MICRO Computer SUPERSERVER 6012P-6 - Manual (Page 12)

S UPER S ERVER 6012P-6 Manual
1-2
! Rackmount hardware (with screws):
Two (2) rack rail assemblies
Six (6) brackets for mounting the rack rails to a rack/telco rack
!
One (1) CD-ROM containing drivers and utilities:
Intel LANDesk Client Manager
ATI Rage XL 8MB PCI graphics controller driver
LAN driver
SCSI driver
!
SuperServer 6012P-6 User's Manual
1-2 Mainboard Features
At the heart of the SuperServer 6012P-6 lies the P4DPR-6GM+, a dual Intel Xeon
processor motherboard designed to provide maximum performance. Below
are the main features of the P4DPR-6GM+.
Chipset
The P4DPR-6GM+ is based on Intel's E7500 chipset, which is a high-perfor-
mance core logic chipset designed for dual-processor servers (See Figure 1-1).
The E7500 chipset consists of four major components: the Memory Controller
Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0 (P64H2) and
the 82808AA Host Channel Adapter (VxB).
The MCH has four hub interfaces, one to communicate with the ICH3 and three
for high-speed I/O communications. The MCH employs a 144-bit wide memory
bus for a PC1600 (DDR-200) memory interface, which provides a total bandwidth
of 3.2 GB/s. The ICH3 interface is a 266 MB/sec point-to-point connection using
an 8-bit wide, 66 MHz base clock at a 4x data transfer rate. The P64H2 interface
is a 1 GB/s point-to-point connection using a 16-bit wide, 66 MHz base clock at
a 8x data transfer rate.
The ICH3 I/O Controller Hub provides various integrated functions, including a
two-channel UDMA100 bus master IDE controller, USB host controllers, an in-
tegrated LAN controller, a System Management Bus controller and an
AC'97 compliant interface.
The P64H2 PCI-X Hub provides a 16-bit connection to the MCH for high-
performance IO capability and the 64-bit PCI-X interface.