Intel PXA26X - Manual (Page 459)

Intel® PXA26x Processor Family Developer’s Manual 12-49
Universal Serial Bus Device Controller
12.6.19 UDC Data Register x (UDDRx), Where x is 4, 9, or 14
Endpoint(x) is a double-buffered isochronous OUT endpoint that is 256 bytes deep. The UDC
generates an interrupt or DMA request when the EOP is received. Because it is double-buffered, up
to two packets of data may be ready. The data can be removed from the UDC via DMA or by a
direct read from the core. If one packet is being removed and the packet behind it has already been
received, the UDC issues a NAK to the host the next time it sends an OUT packet to Endpoint(x).
This NAK condition remains in place until a full packet space is available in the UDC at
Endpoint(x).
12.6.20 UDC Data Register x (UDDRx), Where x is 5, 10, or 15
Endpoint(x) is an interrupt IN endpoint that is 8 bytes deep. Data must be loaded via direct core
writes. Because the USB system is a host initiator model, the host must poll Endpoint 5 to
determine interrupt conditions. The UDC can not initiate the transaction.
Table 12-30. UDC Endpoint x Data Register, Where x is 4, 9, or 14
0h 4060 0400 UDDR4 Read
0h 4060 0900 UDDR9 Read
0h 4060 0E00 UDDR14 Read
Bit 31:8 7 6 5 4 3 2 1 0
Reserved 8-Bit Data
Rese
t
X 0 0 0 0 0 0 0 0
Bits Name Description
7:0 DATA Top of endpoint data currently being read
31:8 — Reserved for future use
Table 12-31. UDC Endpoint x Data Register, Where x is 5, 10, or 15
0h 4060 00A0 UDDR5 Write
0h 4060 00C0 UDDR10 Write
0h 4060 00E0 UDDR15 Write
Bit 31:8 7 6 5 4 3 2 1 0
Reserved 8-Bit Data
Rese
t
X 0 0 0 0 0 0 0 0
Bits Name Description
7:0 DATA Top of endpoint data currently being loaded
31:8 — Reserved for future use