Intel PXA26X - Manual (Page 445)

Intel® PXA26x Processor Family Developer’s Manual 12-35
Universal Serial Bus Device Controller
12.6.7 UDC Endpoint x Control/Status Register (UDCCSx), Where
x is 5, 10, or 15.
The UDC endpoint(x) control status register contains 6 bits that operate endpoint(x), an interrupt
IN endpoint.
12.6.7.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is set if the FIFO does not contain any data bytes and UDCCSx[TSP]
is not set.
Table 12-17. UDC Endpoint x Control Status Register, Where x is 4, 9, or 14
0h 4060 0020 UDCCS4 Read/Write
0h 4060 0034 UDCCS9 Read/Write
0h 4060 0048 UDCCS14 Read/Write
Bit 31:8 7 6 5 4 3 2 1 0
Reserved RSP RNE Reserved Reserved DME ROF RPC RFS
Rese
t
X 0 0 0 0 0 0 0 0
Bits Name Description
0 RFS
RECEIVE FIFO SERVICE (read-only):
0 – Receive FIFO has less than 1 data packet.
1 – Receive FIFO has 1 or more data packets.
1 RPC
RECEIVE PACKET COMPLETE (read/write 1 to clear):
0 – Error/status bits invalid.
1 – Receive packet has been received and error/status bits are valid.
2 ROF
RECEIVE OVERFLOW (read/write 1 to clear):
1 – Isochronous data packets are being dropped from the host because
the receiver is full.
3 DME
DMA ENABLE (read/write):
0 – Send receive interrupt after EOP receive
1 – Send data received interrupt after EOP received and receive FIFO
has < 32 bytes of data
4 —
Reserved
Always reads 0.
5 —
Reserved
Always reads 0.
6 RNE
RECEIVE FIFO NOT EMPTY (read-only):
0 – Receive FIFO empty.
1 – Receive FIFO not empty.
7 RSP
RECEIVE SHORT PACKET (read-only):
1 – Short packet received and ready for reading.
31:8 Reserved Reserved for future use