Intel PXA26X - Manual (Page 458)

12-48 Intel® PXA26x Processor Family Developer’s Manual
Universal Serial Bus Device Controller
12.6.17 UDC Data Register x (UDDRx), Where x is 2, 7, or 12
Endpoint(x) is a double-buffered bulk OUT endpoint that is 64 bytes deep. The UDC generates
either an interrupt or DMA request as soon as the EOP is received. Since it is double buffered, up
to two packets of data may be ready. Via DMA or by direct read from the core, the data can be
removed from the UDC. If one packet is being removed and the packet behind it has already been
received, the UDC will issue a NAK to the host the next time it sends an OUT packet to
endpoint(x). This NAK condition will remain in place until a full packet space is available in the
UDC at Endpoint(x).
12.6.18 UDC Data Register x (UDDRx), Where x is 3, 8, or 13
Endpoint(x) is a double-buffered isochronous IN endpoint that is 256 bytes deep. Data can be
loaded via DMA or direct core writes. Because it-is double buffered, up to two packets of data may
be loaded for transmission.
Table 12-28. UDC Endpoint x Data Register, Where x is 2, 7, or 12
0h 4060 0180 UDDR2 Read
0h 4060 0680 UDDR7 Read
0h 4060 0B80 UDDR12 Read
Bit 31:8 7 6 5 4 3 2 1 0
Reserved 8-Bit Data
Rese
t
X 0 0 0 0 0 0 0 0
Bits Name Description
7:0 DATA Top of endpoint data currently being read
31:8 — Reserved for future use
Table 12-29. UDC Endpoint x Data Register, where x is 3, 8, or 13
0h 4060 0200 UDDR3 Write
0h 4060 0700 UDDR8 Write
0h 4060 0C00 UDDR13 Write
Bit 31:8 7 6 5 4 3 2 1 0
Reserved 8-Bit Data
Rese
t
X 0 0 0 0 0 0 0 0
Bits Name Description
7:0 DATA Top of endpoint data currently being loaded
31:8 — Reserved for future use