Intel I945P - Manual (Page 40)

BIOS
Page 4-6
DRAM Timing Selectable
For setting DRAM Timing, select By SPD to follow Intel PC DDR SDRAM Serial
Presence Detect Specification.
Options: Manual, By SPD.
CAS Latency Time
This item specifies the number of clock cycles needed after a Column Address Strobe
(CAS) signal before data can be read.
Options: 5, 4, 3, 6, Auto.
DRAM RAS# to CAS# Delay
This item sets the timing parameters for the system memory such as the CAS (Column
Address Strobe) and RAS (Row Address Strobe).
Options: 2, 3, 4, 5, 6, Auto.
DRAM RAS# Precharge
This item refers to the number of cycles required to return data to its original
location to close the bank or the number of cycles required to page memory before
the next bank activate command can be issued.
Options: 2, 3, 4, 5, 6, Auto.
Precharge Delay (tRAS)
This item specifies the number of clock cycles needed after a bank active command
before a precharge can occur (sets the minimum RAS pulse width.).
Options: Auto, 4 ~ 15.
System BIOS Cacheable
This item allows the system BIOS to be cached in memory for faster execution.
Options: Disabled, Enabled.
Video BIOS Cacheable
This item allows the video BIOS to be cached in memory for faster execution.
Options: Disabled, Enabled.