Intel GD82559ER User Manual
Page 77
Datasheet
71
Networking Silicon — GD82559ER
9.3.8
Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter Bit Definitions
9.3.9
Register 24: 10BASE-T Receive End of Frame Error Counter Bit
Definitions
9.3.10
Register 25: 10BASE-T Transmit Jabber Detect Counter Bit
Definitions
9.3.11
Register 26: Equalizer Control and Status Bit Definitions
9.3.12
Register 27: PHY Unit Special Control Bit Definitions
Bit(s)
Name
Description
Default
R/W
15:0
Premature End of
Frame
This field contains a 16-bit counter that increments for
each premature end of frame event. The counter
freezes when full and self-clears on read.
--
RO
SC
Bit(s)
Name
Description
Default
R/W
15:0
End of Frame
Counter
This is a 16-bit counter that increments for each end
of frame error event. The counter freezes when full
and self-clears on read.
--
RO
SC
Bit(s)
Name
Description
Default
R/W
15:0
Jabber Detect
Counter
This is a 16-bit counter that increments for each
jabber detection event. The counter freezes when full
and self-clears on read.
--
RO
SC
Bit(s)
Name
Description
Default
R/W
15:0
RFU
Reserved for Future Use
--
RW
Bit(s)
Name
Description
Default
R/W
15:3
Reserved
These bits are reserved and should be set to 0b.
0
RW
2:0
LED Switch
Control
Value
000
001
010
011
100
101
110
111
ACTLED
Activity
Speed
Speed
Activity
Off
Off
On
On
LILED
Link
Collision
Link
Collision
Off
On
Off
On
000
RW