FUJITSU T2000 - Manual (Page 21)

SPARC Enterprise T2000 Server Features 5
Chip-Multitheaded Multicore Processor and
Memory Technology
The UltraSPARC ® T1 multicore processor is the basis of the SPARC Enterprise T2000
server. The UltraSPARC T1 processor is based on chip multithreading (CMT)
technology that is optimized for highly threaded transactional processing. The
UltraSPARC T1 processor improves throughput while using less power and
dissipating less heat than conventional processor designs.
Depending on the model purchased, the processor has four or eight UltraSPARC
cores. Each core equates to a 64-bit execution pipeline capable of running four
threads. The result is that the 8-core processor handles up to 32 active threads
concurrently.
Additional processor components, such as L1 cache, L2 cache, memory access
crossbar, DDR2 memory controllers, and a JBus I/O interface have been carefully
tuned for optimal performance. See
FIGURE 2 .
FIGURE 2 UltraSPARC T1 Multicore Processor Block Diagram
SPARC
core
SPARC
core
SPARC
core
SPARC
core
SPARC
core
SPARC
core
SPARC
core
SPARC
core
Multithreaded pipe
Instruction
cache
Integer
pipeline
Data
cache
Crossbar
Shared L2 cache
DRAM DRAM DRAM DRAM
4 threads